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{{intel title|Cannon Lake|arch}}
+
{{intel title|Cannonlake|arch}}
 
{{microarchitecture
 
{{microarchitecture
 
|atype=CPU
 
|atype=CPU
|name=Cannon Lake
+
|name=Cannonlake
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
|introduction=May 15, 2018
+
|introduction=2017
 
|process=10 nm
 
|process=10 nm
|cores=2
 
|type=Superscalar
 
|oooe=Yes
 
|speculative=Yes
 
|renaming=Yes
 
|stages min=14
 
|stages max=19
 
|decode=5-way?
 
 
|isa=x86-64
 
|isa=x86-64
|extension=MOVBE
+
 
|extension 2=MMX
+
|core name=Cannonlake Y
|extension 3=SSE
+
|core name 2=Cannonlake U
|extension 4=SSE2
 
|extension 5=SSE3
 
|extension 6=SSSE3
 
|extension 7=SSE4.1
 
|extension 8=SSE4.2
 
|extension 9=POPCNT
 
|extension 10=AVX
 
|extension 11=AVX2
 
|extension 12=AES
 
|extension 13=PCLMUL
 
|extension 14=FSGSBASE
 
|extension 15=RDRND
 
|extension 16=FMA3
 
|extension 17=F16C
 
|extension 18=BMI
 
|extension 19=BMI2
 
|extension 20=VT-x
 
|extension 21=VT-d
 
|extension 22=TXT
 
|extension 23=TSX
 
|extension 24=RDSEED
 
|extension 25=ADCX
 
|extension 26=PREFETCHW
 
|extension 27=CLFLUSHOPT
 
|extension 28=XSAVE
 
|extension 29=SGX
 
|extension 30=MPX
 
|extension 31=AVX-512
 
|extension 32=AVX-512F
 
|extension 33=AVX-512CD
 
|extension 34=AVX-512BW
 
|extension 35=AVX-512DQ
 
|extension 36=AVX-512VL
 
|extension 37=AVX-512IFMA
 
|extension 38=AVX-512VBMI
 
|extension 39=SHA
 
|extension 40=UMIP
 
|l1i=32 KiB
 
|l1i per=core
 
|l1i desc=8-way set associative
 
|l1d=32 KiB
 
|l1d per=core
 
|l1d desc=8-way set associative
 
|l2=256 KiB
 
|l2 per=core
 
|l2 desc=4-way set associative
 
|l3=2 MiB
 
|l3 per=core
 
|l3 desc=Up to 16-way set associative
 
|core name 2=Cannon Lake Y
 
 
|predecessor=Kaby Lake
 
|predecessor=Kaby Lake
 
|predecessor link=intel/microarchitectures/kaby lake
 
|predecessor link=intel/microarchitectures/kaby lake
 
|successor=Ice Lake
 
|successor=Ice Lake
|successor link=intel/microarchitectures/ice lake (client)
+
|successor link=intel/microarchitectures/ice lake
|contemporary=Coffee Lake
 
|contemporary link=intel/microarchitectures/coffee lake
 
 
|core names=Yes
 
|core names=Yes
 
|succession=Yes
 
|succession=Yes
 
}}
 
}}
'''Cannon Lake''' ('''CNL''') (formerly '''Skymont''') is a planned [[microarchitecture]] by [[Intel]] as a successor to {{\\|Kaby Lake}}. Cannon Lake is expected to be fabricated using a [[10 nm process]] and is set to be introduced in the second half of [[2018]]. Cannon Lake is the "Process" microarchitecture as part of Intel's {{intel|PAO}} model.
+
'''Cannonlake''' ('''CNL''') (formerly '''Skymont''') is a planned [[microarchitecture]] by [[Intel]] as a successor to {{\\|Kaby Lake}}. Cannonlake is expected to be fabricated using a [[10 nm process]] and is set to be introduced in the fourth quarter of [[2017]]. Cannonlake is the "Process" microarchitecture as part of Intel's {{intel|PAO}} model.
 
 
For mobile, Cannon Lake is expected to be branded as 8th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}. and {{intel|Core i7}} processors.
 
  
== Codenames ==
+
For mobile, Cannonlake is expected to be branded as 8th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}. and {{intel|Core i7}} processors.
{| class="wikitable"
 
|-
 
! Core !! Abbrev !! Description !! Graphics !! Target
 
|-
 
| {{intel|Cannon Lake U|l=core}} || CNL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
 
|}
 
 
 
== Release Dates ==
 
Initial Cannon Lake models were introduced in May 2018 with additional models planned throughout the year.
 
  
 
== Process Technology ==
 
== Process Technology ==
Cannon Lake is manufactured on Intel's [[10 nm process]] (P1274). Intel's 10 nm process is among the first high-volume manufacturing processes to employ [[Self-Aligned Quad Patterning]] (SAQP) (goes under the "Hyper-Scaling" marketing name). Intel's 10nm features a 0.0367 µm² [[SRAM]] bit cell.
+
Cannonlake is manufactured on Intel's [[10 nm process]] (P1274). Intel's 10 nm process is the first high-volume manufacturing process to employ [[Self-Aligned Quad Patterning]] (SAQP) (goes under the "Hyper-Scaling" marketing name). Intel's 10nm features a 0.0367 µm² [[SRAM]] bit cell.
  
 
[[Scaling]]:
 
[[Scaling]]:
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{| class="wikitable"
 
{| class="wikitable"
 
|-
 
|-
! !! Broadwell !! Cannon<br>Lake !! Δ !! rowspan="8" | [[File:intel 10nm fin.png|250px]]
+
! !! Broadwell !! Cannonlake !! Δ !! rowspan="8" | [[File:intel 10nm fin.png|250px]]
 
|-
 
|-
 
| || [[14 nm]] || [[10 nm]] ||
 
| || [[14 nm]] || [[10 nm]] ||
 
|-
 
|-
| Fin Pitch || &nbsp;42 nm || &nbsp;34 nm || 0.81x
+
| Fin Pitch || 42 nm || 34 || 0.81x
 
|-
 
|-
| Fin Width​ || &nbsp;&nbsp;8 nm || &nbsp;&nbsp;7 nm || 0.88x
+
| Fin Width​ || 8 nm || ? nm || ?x
 
|-
 
|-
| Fin Height​ || &nbsp;42 nm || &nbsp;53 nm || 1.24x
+
| Fin Height​ || 42 nm || 53 nm || 1.24x
 
|-
 
|-
| Gate Pitch || &nbsp;70 nm || &nbsp;54 nm || 0.77x
+
| Gate Pitch || 70 nm || 54 nm || 0.77x
 
|-
 
|-
| Interconnect Pitch || &nbsp;52 nm || &nbsp;36 nm || 0.69x
+
| Interconnect Pitch || 52 nm || 36 nm || 0.69x
 
|-
 
|-
 
| Cell Height || 399 nm || 272 nm || 0.68x
 
| Cell Height || 399 nm || 272 nm || 0.68x
 
|}
 
|}
  
== Compiler support ==
+
== Codenames ==
Support for Cannon Lake was added in GCC 8.1 and LLVM 6.0.
+
{{future information}}
 +
 
 
{| class="wikitable"
 
{| class="wikitable"
 
|-
 
|-
! Compiler !! Arch-Specific || Arch-Favorable
+
! Core !! Abbrev !! Description !! Graphics !! Target
 
|-
 
|-
| [[ICC]] || <code>-march=cannonlake</code> || <code>-mtune=cannonlake</code>
+
| {{intel|Cannonlake Y|l=core}} || CNL-Y || Extremely low power || GT2 || 2-in-1s detachable, tablets, and computer sticks
 
|-
 
|-
| [[GCC]] || <code>-march=cannonlake</code> || <code>-mtune=cannonlake</code>
+
| {{intel|Cannonlake U|l=core}} || CNL-U || Ultra-low Power || GT2/GT3 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
 
|-
 
|-
| [[LLVM]] || <code>-march=cannonlake</code> || <code>-mtune=cannonlake</code>
+
| {{intel|Cannonlake H|l=core}} || CNL-H || High-performance Graphics || GT2/GT3 || Ultimate mobile performance, mobile workstations
|-
+
|-  
| [[Visual Studio]] || <code>?</code> || <code>?</code>
+
| {{intel|Cannonlake S|l=core}} || CNL-S || Performance-optimized lifestyle || GT2/GT3 || Desktop performance to value, AiOs, and minis
|}
+
|-  
 
+
| {{intel|Cannonlake DT|l=core}} || CNL-DT || Workstation || GT2 || Workstations & entry-level servers
=== CPUID ===
 
{| class="wikitable tc1 tc2 tc3 tc4"
 
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
 
|-
 
| rowspan="2" | {{intel|Cannon Lake U|U|l=core}} || 0 || 0x6 || 0x6 || 0x6
 
|-
 
| colspan="4" | Family 6 Model 102
 
 
|}
 
|}
  
 
== Architecture ==
 
== Architecture ==
=== Key changes from {{\\|Skylake (client)|Skylake}} ===
+
{{empty section}}
 +
=== Key changes from {{\\|Kaby Lake}} ===
 
* [[10 nm process]] (from [[14 nm]])
 
* [[10 nm process]] (from [[14 nm]])
 
* {{\\|Palm Cove|Palm Cove core}} (from {{\\|Skylake (client)|Skylake}})
 
** ''See {{\\|Palm Cove}} for microarchitectural details and changes''
 
 
 
* Mainstream chipset
 
* Mainstream chipset
** {{intel|Union Point|200 Series chipset|l=chipset}} → {{intel|Cannon Point|300 Series chipset|l=chipset}}
+
** {{intel|Union Point|200 Series chipset|l=chipset}} → 300 Series chipset
 
+
*** Integrated Programmable (Open FW SDK) Quad-Core Audio DSP
* Mobile Processors
+
*** Soundwire Digital Audio Interface
** LPDDR4/LPDDR4X memory support (from LPDDR3)
+
*** Integrated USB 3.1 (10 Gib/s)
*** Rates up to 2400 MT/s
+
**** Up to 6 ports
 +
*** Integrated Intel wireless controller ([[IEEE 802.11ac]])
 +
*** Integrated SDXC 3.0 controller
 +
*** Thunderbolt 3.0(Titan Ridge) with DisplayPort 1.4 support
 +
*** C10 & S0ix Support for Modern Standby
  
 
* {{intel|Gen9.5|l=arch}} → {{intel|Gen10|l=arch}} graphics
 
* {{intel|Gen9.5|l=arch}} → {{intel|Gen10|l=arch}} graphics
 
* {{intel|Gen10|l=arch}} GPUs
 
* {{intel|Gen10|l=arch}} GPUs
** HD Graphics 6xx (GT1) '''→''' UHD Graphics 7xx (GT1) (24 Execution Units, 2x EUs from {{\\|Skylake}})
+
** {{intel|HD Graphics 610}} '''→''' {{intel|HD Graphics 710}} (24 Execution Units, 2x EUs from {{\\|Kaby Lake}})
** HD Graphics 6xx (GT2) '''→''' UHD Graphics 7xx (GT2) (40 Execution Units, 1.7x EUs from {{\\|Skylake}})
+
** {{intel|HD Graphics 615}} '''→''' {{intel|HD Graphics 715}} (40 Execution Units, 1.7x EUs from {{\\|Kaby Lake}})
 
+
** {{intel|HD Graphics 620}} '''→''' {{intel|HD Graphics 720}} (40 Execution Units, 1.7x EUs from {{\\|Kaby Lake}})
* New Integration
+
** {{intel|HD Graphics 630}} '''→''' {{intel|HD Graphics 730}} (40 Execution Units, 1.7x EUs from {{\\|Kaby Lake}})
** New Gaussian Neural Accelerator 1.0 (Unclear to what extent)
+
** {{intel|HD Graphics P630}} '''→''' {{intel|HD Graphics P730}} (40 Execution Units, 1.7x EUs from {{\\|Kaby Lake}})
 
+
** {{intel|Iris Plus Graphics 640}} '''→''' {{intel|Iris Plus Graphics 740}} (unknown change)
====New instructions ====
+
** {{intel|Iris Plus Graphics 650}} '''→''' {{intel|Iris Plus Graphics 750}} (unknown change)
Cannon Lake introduced a number of {{x86|extensions|new instructions}}. See {{intel|palm cove#New instructions|Palm Cove § New Instructions|l=arch}} for details.
 
 
 
=== Block Diagram ===
 
 
 
==== Entire SoC Overview ====
 
[[File:cannon lake soc block diagram.svg|800px]]
 
 
 
==== Individual Core ====
 
See {{intel|Palm Cove#Block Diagram|Palm Cove § Block Diagram|l=arch}}.
 
  
==== Gen11 Graphics ====
+
== All Cannonlake Chips ==
See {{intel|Gen10#Block Diagram|Gen10 Graphics § Block Diagram|l=arch}}.
 
 
 
== Die ==
 
=== Dual-core ===
 
* [[10 nm process]]
 
* [[13 metal layers]]
 
* ~8.2 mm x ~8.6 mm
 
* ~70.52 mm² die size
 
* 2 CPU cores + 40 GPU EUs
 
 
 
== All Cannon Lake Chips ==
 
 
<!-- NOTE:  
 
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           This table is generated automatically from the data in the actual articles.
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           created and tagged accordingly.
  
           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
 
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{{comp table start}}
 
{{comp table start}}
<table class="comptable sortable tc4 tc5 tc6">
+
<table class="comptable sortable tc18 tc19 tc20 tc21 tc22 tc23">
{{comp table header|main|7:List of Cannon Lake-based Processors}}
+
<tr class="comptable-header"><th>&nbsp;</th><th colspan="23">Cannonlake Chips</th></tr>
{{comp table header|cols|Price|Launched|Cores|Threads|TDP|%Frequency|%Turbo}}
+
<tr class="comptable-header"><th>&nbsp;</th><th colspan="13">Main processor</th><th colspan="3">IGP</th><th colspan="7">Major Feature Diff</th></tr>
{{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Cannon Lake]]
+
<tr class="comptable-header"><th class="unsortable">Model</th><th>Launched</th><th>Price</th><th>Family</th><th>Platform</th><th>Core</th><th>C</th><th>T</th><th>L3$</th><th>L4$</th><th>TDP</th><th>Freq</th><th>Turbo</th><th>Max Mem</th><th>Name</th><th>Freq</th><th>Turbo</th><th>{{intel|turbo boost|TBT}}</th><th>HT</th><th>AVX2</th><th>TXT</th><th>TSX</th><th>vPro</th><th>VT-d</th></tr>
 +
<tr class="comptable-header comptable-header-sep"><th>&nbsp;</th><th colspan="23">[[Uniprocessors]]</th></tr>
 +
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Cannonlake]] [[max cpu count::1]]
 
  |?full page name
 
  |?full page name
 
  |?model number
 
  |?model number
 +
|?first launched
 
  |?release price
 
  |?release price
  |?first launched
+
  |?microprocessor family
 +
|?platform
 +
|?core name
 
  |?core count
 
  |?core count
 
  |?thread count
 
  |?thread count
 +
|?l3$ size
 +
|?l4$ size
 
  |?tdp
 
  |?tdp
 
  |?base frequency#GHz
 
  |?base frequency#GHz
 
  |?turbo frequency (1 core)#GHz
 
  |?turbo frequency (1 core)#GHz
 +
|?max memory#GiB
 +
|?integrated gpu
 +
|?integrated gpu base frequency
 +
|?integrated gpu max frequency
 +
|?has intel turbo boost technology 2_0
 +
|?has simultaneous multithreading
 +
|?has advanced vector extensions 2
 +
|?has intel trusted execution technology
 +
|?has transactional synchronization extensions
 +
|?has intel vpro technology
 +
|?has_intel_vt-d_technology
 
  |format=template
 
  |format=template
 
  |template=proc table 3
 
  |template=proc table 3
  |userparam=9
+
|searchlabel=
 +
|sort=microprocessor family, model number
 +
|order=asc,asc
 +
  |userparam=25:19
 
  |mainlabel=-
 
  |mainlabel=-
 +
|limit=100
 
}}
 
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[microarchitecture::Cannon Lake]]}}
+
<tr><th>&nbsp;</th><th colspan="23"><span style="font-size: 20px;">No Cannonlake Chips have been released yet.</span></th></tr>
 +
{{comp table count|ask=[[Category:microprocessor models by intel]][[instance of::microprocessor]][[microarchitecture::Cannonlake]]}}
 
</table>
 
</table>
 
{{comp table end}}
 
{{comp table end}}
  
 
== References ==
 
== References ==
* Some information was obtained directly from Intel.
 
 
* Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.
 
* Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.
  
 
== See also ==
 
== See also ==
 
* AMD's {{amd|Zen|l=arch}}
 
* AMD's {{amd|Zen|l=arch}}

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