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Broadwell is designed to be manufactured using [[14 nm]] Tri-gate [[FinFET]] transistors. This correlates to 8 nm Fin width and a 42 nm Fin pitch (shown below). SRAM cell is at 0.0706 µm² and 0.0499 µm² for high performance and high density.
 
Broadwell is designed to be manufactured using [[14 nm]] Tri-gate [[FinFET]] transistors. This correlates to 8 nm Fin width and a 42 nm Fin pitch (shown below). SRAM cell is at 0.0706 µm² and 0.0499 µm² for high performance and high density.
  
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Scaling:
  
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[[Scaling]]:
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[[File:intel 14nm gate.png|215px|left]]
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{| class="wikitable"
 
{| class="wikitable"
 
|-
 
|-
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! !! Haswell !! Broadwell !! Δ !! rowspan="8" | [[File:intel 14nm fin.png|250px]]
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! !! Haswell !! Broadwell !! Δ
 
|-
 
|-
 
| || [[22 nm]] || [[14 nm]] ||
 
| || [[22 nm]] || [[14 nm]] ||
 
|-
 
|-
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| Fin Pitch || 60 nm || 42 || 0.70x
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| Fin Pitch || 60 nm || 42 nm || 0.70x
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|-
 
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| Fin Width​ || 8 nm || 8 nm || 1x
 
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|-
 
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| Fin Height​ || 34 nm || 42 nm || 1.24x
 
 
|-
 
|-
 
| Gate Pitch || 90 nm || 70 nm || 0.78x
 
| Gate Pitch || 90 nm || 70 nm || 0.78x
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| Cell Height || 840 nm || 399 nm || 0.48x
 
| Cell Height || 840 nm || 399 nm || 0.48x
 
|}
 
|}
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{{clear}}
  
 
== Architecture==
 
== Architecture==

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Facts about "Broadwell - Microarchitectures - Intel"
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codenameBroadwell +
core count2 +, 4 +, 6 +, 8 +, 10 +, 12 +, 14 +, 16 +, 18 +, 20 + and 22 +
designerIntel +
first launchedOctober 2014 +
full page nameintel/microarchitectures/broadwell (client) +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameBroadwell +
pipeline stages (max)19 +
pipeline stages (min)14 +
process14 nm (0.014 μm, 1.4e-5 mm) +