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=== Overview ===
 
=== Overview ===
Bonnell's architecture shares very little in common with other Intel designs. To achieve the strict ultra-low power objects, Bonnell features a very slimmed down design discarding many high-performance techniques used by Intel's high-performance architectures such as aggressive [[speculative execution]], [[out-of-order]] execution, and µop transformation.
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Bonnell's architecture shares very little in common with other Intel designs. To achieve the strict ultra-low power objects, Bonnell features a very slimmed own design discarding many high-performance techniques used by Intel's high-performance architectures such as aggressive [[speculative execution]], [[out-of-order]] execution, and µop transformation.
  
 
Part of the design requirement was that Bonnell retain full [[x86]] compatibility, up to the latest extension - at one tenth of the power consumption of the {{\\|Pentium M}}. This meant any software is now 100% compatible but it forced engineers to deal with all the baggage the architecture brought along. The decision to offer full compatibility brought its own set of benefits such as access to the largest software code base in the world, including the ability to run any other [[x86]] operating system unmodified. At the same time it forced the design team to resort to other means of reducing power.  
 
Part of the design requirement was that Bonnell retain full [[x86]] compatibility, up to the latest extension - at one tenth of the power consumption of the {{\\|Pentium M}}. This meant any software is now 100% compatible but it forced engineers to deal with all the baggage the architecture brought along. The decision to offer full compatibility brought its own set of benefits such as access to the largest software code base in the world, including the ability to run any other [[x86]] operating system unmodified. At the same time it forced the design team to resort to other means of reducing power.  

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