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Difference between revisions of "intel/microarchitectures/alder lake"
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|introduction=2021 | |introduction=2021 | ||
|process=10 nm | |process=10 nm | ||
| + | |cores=8+8 | ||
| + | |cores 2=6+8 | ||
| + | |cores 3=6+0 | ||
|isa=x86-64 | |isa=x86-64 | ||
| + | |core name=Golden Cove | ||
| + | |core name 2=Gracemont | ||
|predecessor=Tiger Lake | |predecessor=Tiger Lake | ||
|predecessor link=intel/microarchitectures/tiger lake | |predecessor link=intel/microarchitectures/tiger lake | ||
|predecessor 2=Rocket Lake | |predecessor 2=Rocket Lake | ||
|predecessor 2 link=intel/microarchitectures/rocket lake | |predecessor 2 link=intel/microarchitectures/rocket lake | ||
| − | |successor= | + | |successor=Raptor Lake |
| − | |successor link=intel/microarchitectures/ | + | |successor link=intel/microarchitectures/raptor lake |
}} | }} | ||
'''Alder Lake''' ('''ADL''') is [[Intel]]'s successor to {{\\|Tiger Lake}}, a [[10 nm]] [[microarchitecture]] for mainstream workstations, desktops, and mobile devices. | '''Alder Lake''' ('''ADL''') is [[Intel]]'s successor to {{\\|Tiger Lake}}, a [[10 nm]] [[microarchitecture]] for mainstream workstations, desktops, and mobile devices. | ||
| Line 20: | Line 25: | ||
{{future information}} | {{future information}} | ||
== Process Technology== | == Process Technology== | ||
| + | Intel is planning Alder Lake to be built on an improved 10 nm Enhanced Superfin node, or 10 nm+++. This will be the case for both the powerful Golden Cove cores, and Gracemont cores. | ||
== History == | == History == | ||
| + | In January 2021 Intel teased Alder Lake in their CES 2021 speech. | ||
== Architecture == | == Architecture == | ||
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* Core | * Core | ||
** Hybrid Golden Cove(big core) & Gracemont(small core) microarchitecture | ** Hybrid Golden Cove(big core) & Gracemont(small core) microarchitecture | ||
| − | ** | + | ** At least 20% IPC improvements |
| − | ** | + | ** 10 nm Enhanced SuperFin(ESF) node |
| + | * Memory | ||
| + | ** Support for DDR5 | ||
| + | ** Speeds of at least 4800MHz, up to 5600MHz | ||
| + | * Improved power delivery system | ||
Revision as of 10:16, 24 May 2021
| Edit Values | |
| Alder Lake µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2021 |
| Process | 10 nm |
| Core Configs | "+8" can not be assigned to a declared number type with value 8. 8+8, "+8" can not be assigned to a declared number type with value 6. 6+8, "+0" can not be assigned to a declared number type with value 6. 6+0 |
| Instructions | |
| ISA | x86-64 |
| Cores | |
| Core Names | Golden Cove, Gracemont |
| Succession | |
Alder Lake (ADL) is Intel's successor to Tiger Lake, a 10 nm microarchitecture for mainstream workstations, desktops, and mobile devices.
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
Process Technology
Intel is planning Alder Lake to be built on an improved 10 nm Enhanced Superfin node, or 10 nm+++. This will be the case for both the powerful Golden Cove cores, and Gracemont cores.
History
In January 2021 Intel teased Alder Lake in their CES 2021 speech.
Architecture
Key changes from Tiger Lake
- Core
- Hybrid Golden Cove(big core) & Gracemont(small core) microarchitecture
- At least 20% IPC improvements
- 10 nm Enhanced SuperFin(ESF) node
- Memory
- Support for DDR5
- Speeds of at least 4800MHz, up to 5600MHz
- Improved power delivery system
Facts about "Alder Lake - Microarchitectures - Intel"
| codename | Alder Lake + |
| designer | Intel + |
| first launched | 2021 + |
| full page name | intel/microarchitectures/alder lake + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Alder Lake + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |
