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Difference between revisions of "intel/microarchitectures/airmont"
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== Architecture==
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Airmont is for the most part identical to {{intel|Silvermont}} with some higher number of execution units to the GPU in some of the higher-end models.
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=== Key changes from {{intel|Silvermont}} ===
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* DTLB table size doubled (128 entries -> 256 entries)
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* L2 latency increased
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* Reorder Buffer was increased (from 32 entries to 48)
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* Gen 8 GPUs
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=== Block Diagram ===
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[[File:silvermont block.png]]
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=== Memory Hierarchy ===
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* Cache
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** Hardware prefetchers
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** L1 Cache:
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*** 32 KB 8-way [[set associative]] instruction, 64 B line size
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*** 24 KB 6-way set associative data, 64 B line size
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*** Per core
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** L2 Cache:
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*** 1 MB 16-way set associative, 64 B line size
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*** Per 2 cores
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** L3 Cache:
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*** No level 3 cache
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** RAM
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*** Maximum of 1GB, 2 GB, and 4 GB
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*** dual 32-bit channels, 1 or 2 ranks per channel
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=== Multithreading ===
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Silvermont dropped support for Intel Hyper-Threading Technology.
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=== Pipeline ===
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{{main|intel/microarchitectures/silvermont#Pipeline|l1=Silvermont's Pipeline}}
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Airmont's pipeline is identical to {{intel|Silvermont|Silvermont's}}.
 +
 +
[[File:silvermont pipeline.svg]]
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== Cores ==
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* {{intel|Cherry Trail}} - SoCs for Smartphones/Tablets
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* {{intel|Braswell}} - SoCs for low-end PCs

Revision as of 23:04, 9 April 2016

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Airmont µarch
General Info
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Airmont is Intel's 14 nm microarchitecture for the Atom family of system on chips. Introduced in 2015, Airmont is a shrink of Silvermont.

Codenames

Platform Core Target
Cherry Trail Cherry Trail Smartphones, Tablets
Braswell Braswell Tablets, PCs

Architecture

Airmont is for the most part identical to Silvermont with some higher number of execution units to the GPU in some of the higher-end models.

Key changes from Silvermont

  • DTLB table size doubled (128 entries -> 256 entries)
  • L2 latency increased
  • Reorder Buffer was increased (from 32 entries to 48)
  • Gen 8 GPUs

Block Diagram

silvermont block.png

Memory Hierarchy

  • Cache
    • Hardware prefetchers
    • L1 Cache:
      • 32 KB 8-way set associative instruction, 64 B line size
      • 24 KB 6-way set associative data, 64 B line size
      • Per core
    • L2 Cache:
      • 1 MB 16-way set associative, 64 B line size
      • Per 2 cores
    • L3 Cache:
      • No level 3 cache
    • RAM
      • Maximum of 1GB, 2 GB, and 4 GB
      • dual 32-bit channels, 1 or 2 ranks per channel

Multithreading

Silvermont dropped support for Intel Hyper-Threading Technology.

Pipeline

Main article: Silvermont's Pipeline

Airmont's pipeline is identical to Silvermont's.

silvermont pipeline.svg

Cores