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Loihi
General Info
Designer	Intel
Manufacturer	Intel
Market	Artificial Intelligence
Introduction	September 25, 2017 (announced) January, 2018 (launched)
Shop	Amazon
Microarchitecture
Process	14 nm
Transistors	2,070,000,000
Technology	CMOS
Die	60 mm²
Vcore	0.50 V-1.25 V

Loihi (pronounced low-ee-hee) is a neuromorphic research test chip designed by Intel Labs that uses a asynchronous spiking neural network (SNN) to implement adaptive self-modifying event-driven fine-grained parallel computations used to implement learning and inference with high efficiency. The chip is a 128-neuromorphic cores many-core IC fabricated on Intel's 14 nm process.

The chip is named after the Loihi as a play-on-words - Loihi is an emerging Hawaiian submarine volcano that is set to surface one day.

Overview

Announced in September 2017, Loihi is predominantly a research chip meaning performance characteristics are not guaranteed. Loihi consists of a asynchronous spiking neural network (SNN) meaning instead of manipulating signals, the chip sends spikes along activate synapses. Connections are asynchronous and highly timed based. Neuromorphic cores containing many neurons are interlinked and receive spikes from elsewhere in the network. When received spikes accumulate for a certain period of time and reach a set threshold, the core will fire off its own spikes to its connected neurons. Preceding spikes reinforce each other and the neuron connections while spikes that follows will inhibit the connection, declining the connectivity until all activities are halted.

The chip was initially tested and simulated using FPGAs. Actual silicon implementations arrived in late November. Loihi is fabricated on Intel's 14 nm process and has a total of 130,000 artificial neurons and 130 million synapses. In addition to the 128 neuromorphic cores, there are 3 managing Lakemont cores.

Architecture

The chip consists of a many-core mesh of 128 neuromorphic cores, three Lakemont x86 cores (Quark), and an off-chip communication interface that allows the chip to scale out to many other chips in the four planar directions (as shown on the right). The implemented mesh protocol supports up to 4,096 on-chip cores and up to 16,384 chips.

The chip itself implements of a fully asynchronous many-core mesh of 128 neuromorphic cores. It implements a spiking neural network (SNN) whereby at any given time one or more of the implemented neurons may send out an impulse (i.e., spike) to its neighbors though the directed links (synapses). All neurons have a local state with their own set of rules that affects their evolution and the timing of spike generation. Interaction is entirely asynchronous, sporadic, and independent of any other neuron on the network. Core-to-core communication is done in using packetized messages with write, read request, and read response messages for core management and x86-to-x86 messaging, spike messages, and barrier messages (for synchronization).

Neuromorphic Core

Loihi implements 128 neuromorphic cores, each containing 1,024 primitive spiking neural units grouped into tree-like structures in order to simplify the implementation. Each of those groups share the same fan-in and fan-out connections, configuration, and state variables in ten architectural memories.

The operation itself is fairly straightforward, once enough spikes accumulate and exceed the predefined threshold level, a spike message is created and sent out to various other groups in various destination cores.

Each core also contains a "learning engine" that can be programmed to adopt to the network parameters during operation such as the spike timings and their impact. This makes the chip more flexible as it allows various paradigms such as supervisor/non-supervisor and reinforcing/reconfigurablity without requiring any particular approach. The choice for higher flexibility is intentional in order to defer various architectural decisions that could be detrimental to research.

Neural Unit

Loihi implements a variant of the current-based synapse (CUBA) leaky integrate-and-fire neuron model with two internal state variables:

• Synaptic response current - the weighted sum of the input spikes and a constant bias
• Membrane potential - a leaky (i.e. weakens over time) spike potential function that sends out a spike when the potential passes the firing threshold

It's worth noting that since Loihi is a digital architecture, the above continuous functions are approximated using discrete a timestep whereby all neurons maintain a timestemp synchronized throughout the entire chip. This is needed in order to enable well-defined behaviors.

Die

Floorplan

• 14 nm process
• 2,070,000,000 transistors
  • 128 neuromorphic cores + 3 x86 cores
• 60 mm² die size

References

• Jim Held, Intel Fellow & Director Emerging Technologies Research, Intel Labs, HPC Developer Conference 2017 ("Leading The Evolution of Compute: Neuromorphic and Quantum Computing").

See also

• TrueNorth