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==== Self-learning ==== | ==== Self-learning ==== | ||
− | Each core contains a "learning engine" (marked in the block diagram above as 'learning') that can be programmed to adapt to the network parameters during operation such as the spike timings and their impact. It does this by updating the synaptic weights using the 4-bit microcode-programmed learning rules that are specifically associated with that synapse. Updates (or 'learning') is done at each learning epoch, a period of time that is globally preconfigured per core. This makes the chip more flexible as it allows various paradigms such as supervisor/non-supervisor and reinforcing/reconfigurability without requiring any particular approach. The choice for higher flexibility is intentional in order to defer various architectural decisions that could be detrimental to research. | + | Each core also contains a "learning engine" (marked in the block diagram above as 'learning') that can be programmed to adapt to the network parameters during operation such as the spike timings and their impact. It does this by updating the synaptic weights using the 4-bit microcode-programmed learning rules that are specifically associated with that synapse. Updates (or 'learning') is done at each learning epoch, a period of time that is globally preconfigured per core. This makes the chip more flexible as it allows various paradigms such as supervisor/non-supervisor and reinforcing/reconfigurability without requiring any particular approach. The choice for higher flexibility is intentional in order to defer various architectural decisions that could be detrimental to research. |
===== Programming ===== | ===== Programming ===== |
Facts about "Loihi - Intel"
back image | + |
core voltage (max) | 1.25 V (12.5 dV, 125 cV, 1,250 mV) + |
core voltage (min) | 0.5 V (5 dV, 50 cV, 500 mV) + |
designer | Intel + |
die area | 60 mm² (0.093 in², 0.6 cm², 60,000,000 µm²) + |
first announced | September 25, 2017 + |
first launched | January 2018 + |
full page name | intel/loihi + |
instance of | neuromorphic chip + |
ldate | January 2018 + |
main image | + |
manufacturer | Intel + |
market segment | Artificial Intelligence + |
max cpu count | 16,384 + |
name | Loihi + |
neuron count | 131,072 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
smp max ways | 16,384 + |
synapse count | 130,000,000 + |
technology | CMOS + |
transistor count | 2,070,000,000 + |