Semiconductor & Computer Engineering
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The scaling boosters affect both the width and height of the cells. When introduced at their [[10 nm]] node, Intel reported a cell height reduction of 10% for the introduction of COAG in for the width of the cells, Intel reported a 20% reduction in cell area for moving to a [[single diffusion break|SDB]]. | The scaling boosters affect both the width and height of the cells. When introduced at their [[10 nm]] node, Intel reported a cell height reduction of 10% for the introduction of COAG in for the width of the cells, Intel reported a 20% reduction in cell area for moving to a [[single diffusion break|SDB]]. | ||
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[[Category:device fabrication]] | [[Category:device fabrication]] | ||
Revision as of 22:10, 17 June 2018
Hyper Scaling is an umbrella marketing term used by Intel to describe a collection of scaling boosters used in the fabrication process of extremely high-density CMOS logic, starting with their 14 nm node.
Overview
For their 10 nm lithography process, Intel aimed at a 2.7x transistor compaction ratio over their 14 nm node. In order to reach such density increase, Intel had to resort to additional scaling boosters beyond traditional scaling nobs such as the gate pitch and cell height. While not all the boosters are unique to Intel, their 10nm process was the first high-volume manufacturing process to incorporate all those enablers at once.
Hyper Scaling incorporates the following technologies:
- self-aligned quad patterning (SAQP)
- single dummy gate (SDG)
- self-aligned diffusion contacts
- contact over active gate (COAG)
The scaling boosters affect both the width and height of the cells. When introduced at their 10 nm node, Intel reported a cell height reduction of 10% for the introduction of COAG in for the width of the cells, Intel reported a 20% reduction in cell area for moving to a SDB.
