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| | {{intel title|DL Boost}} | | {{intel title|DL Boost}} |
| − | '''DL Boost Technology''' ('''deep learning boost''') is an umbrella marketing term used by [[Intel]] for a collection of technologies designed for the [[acceleration]] of AI workloads, including both inference and training. | + | '''DL Boost''' is a marketing term used by [[Intel]] that encompasses a number of [[x86]] technologies designed to [[accelerate]] AI workloads. |
| − | | |
| − | == Overview ==
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| − | '''DL Boost''' is a term used by [[Intel]] to describe a set of features on their microprocessors designed to accelerate AI workloads. The term was first introduced with {{intel|Cascade Lake|l=arch}} but has since been extended further with more capabilities in newer microarchitectures.
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| − | DL Boost includes the following features:
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| − | * {{x86|AVX512_VNNI|AVX-512 Vector Neural Network Instructions}} (AVX512_VNNI) - an instruction set extension that introduces reduced-precision (8-bit and 16-bit) multiply-accumulate for the acceleration of inference. VNNI was first introduced with {{intel|Cascade Lake|l=arch}} (server) and {{intel|Ice Lake (Client)|Ice Lake|l=arch}} (Client)
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| − | * {{x86|AVX512_BF16|AVX-512 BFloat16 Instructions}} (AVX512_BF16) - an instruction set extension for converting to [[bfloat16]] and then performing multiply-accumulate on such values for the acceleration of both inference and training. BG16 was first introduced with {{intel|Cooper Lake|l=arch}}.
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| − | * {{x86|AMX|Advanced Matrix Extension}} (AMX) - an extension that introduces a matrix register file and matrix operations. AMX was first introduced with {{intel|Sapphire Rapids|l=arch}}.
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| − | | |
| − | == Implementations ==
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| − | {| class="wikitable"
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| − | |-
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| − | ! Microarchitecture !! {{x86|AVX512_VNNI}} !! {{x86|AVX512_BF16}} !! {{x86|AMX}}
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| − | |-
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| − | ! colspan="4" | Client
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| − | |-
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| − | | {{intel|Ice Lake (Client)|l=arch}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}}
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| − | |-
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| − | ! colspan="4" | Server
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| − | |-
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| − | | {{intel|Cascade Lake|l=arch}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}}
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| − | |-
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| − | | {{intel|Cooper Lake|l=arch}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
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| − | |-
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| − | | {{intel|Ice Lake (Server)|l=arch}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}}
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| − | |-
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| − | | {{intel|Sapphire Rapids|l=arch}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}}
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| − | |-
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| − | | {{intel|Granite Rapids|l=arch}} || {{tchk|some|TBD}} || {{tchk|some|TBD}} || {{tchk|some|TBD}}
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| − | |-
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| − | | {{intel|Diamond Rapids|l=arch}} || {{tchk|some|TBD}} || {{tchk|some|TBD}} || {{tchk|some|TBD}}
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| − | |}
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| − | | |
| − | == See also ==
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| − | * [[bfloat16]]
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| − | * [[Neural processors]]
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| − | * [[Acceleration]]
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| | [[category:intel]] | | [[category:intel]] |
