From WikiChip
Editing intel/crystal well
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 1: | Line 1: | ||
{{intel title|Crystal Well}} | {{intel title|Crystal Well}} | ||
− | '''[[ | + | '''[[codename::Crystal Well]]''' is the codename for the L4 cache, a discrete [[eDRAM]] silicon die, which is featured in the high-end [[Iris Pro]]-equipped Intel [[Haswell]] microprocessors. The eDRAM silicon die is separate from the main [[Haswell]] die but is packaged together with it. Crystal Well based processors started shipping in the third quarter of 2013. |
== Details == | == Details == |
Facts about "Crystal Well - Intel"
instance of | codename + |
manufacturer | Intel + |
name | Crystal Well + |