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** {{intel|HD Graphics 510}} (Gen 9.5 LP GT1), {{intel|HD Graphics 520}} ({{intel|Gen9.5|l=arch}} GT2), or {{intel|Iris Graphics 540}}/{{intel|Iris Graphics 550|550}} ({{intel|Gen9.5|l=arch}} GT3e) | ** {{intel|HD Graphics 510}} (Gen 9.5 LP GT1), {{intel|HD Graphics 520}} ({{intel|Gen9.5|l=arch}} GT2), or {{intel|Iris Graphics 540}}/{{intel|Iris Graphics 550|550}} ({{intel|Gen9.5|l=arch}} GT3e) | ||
** 3 independent displays supported | ** 3 independent displays supported | ||
− | ** Base frequency of | + | ** Base frequency of 350 MHz |
− | ** Burst frequency of 1-1. | + | ** Burst frequency of 1-1.15 GHz |
{{clear}} | {{clear}} |
Facts about "Skylake U - Cores - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Skylake U - Cores - Intel#package + |
designer | Intel + |
first announced | September 1, 2015 + |
first launched | September 27, 2015 + |
instance of | core + |
isa | x86-64 + |
main image | + and + |
main image caption | 3-die config Iris Plus SKL-U (with OPC) + and 2-die config SKL-U + |
manufacturer | Intel + |
microarchitecture | Skylake + |
name | Skylake U + |
package | FCBGA-1356 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |