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== Overview == | == Overview == | ||
− | Skylake SP processors are based on Intel's {{intel|Skylake (server)|Skylake|l=arch}} server configuration which incorporates a very large number of enhancements and improvements over its predecessor. Those processors support between two and eight-way multi-processing (the exact support depends on the Xeon family) and with all models supporting hex-chanel 768 GiB of DDR4 ECC memory or 1.5 | + | Skylake SP processors are based on Intel's {{intel|Skylake (server)|Skylake|l=arch}} server configuration which incorporates a very large number of enhancements and improvements over its predecessor. Those processors support between two and eight-way multi-processing (the exact support depends on the Xeon family) and with all models supporting hex-chanel 768 GiB of DDR4 ECC memory or 1.5 GiB for extended memory models. |
Skylake SP processors utilize the new {{intel|FCLGA-3647}} package (which makes use of "Socket P"). Those use the {{intel|Lewisburg}} chipset ({{intel|Platform Controller Hub|HUB}}) via 4 PCIe3 lanes using Intel's proprietary {{intel|Direct Media Interface}} 3.0 (DMI 3.0), allowing for 8 GT/s transfer rate per lane. When in multi-socket configuration, the microprocessor is connected to the other processors via the {{intel|Ultra Path Interconnect}} (UPI) links which Intel introduced with Skylake SP as well, replacing and obsoleting the older {{intel|QuickPath Interconnect}} (QPI) operating. Depending on the model, there may be either two or three UPI links inter-linking each socket (for more details see {{intel|skylake (server)#Scalability|Skylake § Scalability|l=arch}}). | Skylake SP processors utilize the new {{intel|FCLGA-3647}} package (which makes use of "Socket P"). Those use the {{intel|Lewisburg}} chipset ({{intel|Platform Controller Hub|HUB}}) via 4 PCIe3 lanes using Intel's proprietary {{intel|Direct Media Interface}} 3.0 (DMI 3.0), allowing for 8 GT/s transfer rate per lane. When in multi-socket configuration, the microprocessor is connected to the other processors via the {{intel|Ultra Path Interconnect}} (UPI) links which Intel introduced with Skylake SP as well, replacing and obsoleting the older {{intel|QuickPath Interconnect}} (QPI) operating. Depending on the model, there may be either two or three UPI links inter-linking each socket (for more details see {{intel|skylake (server)#Scalability|Skylake § Scalability|l=arch}}). | ||
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* Hexa-channel memory | * Hexa-channel memory | ||
− | ** 768 GiB / 1.5 | + | ** 768 GiB / 1.5 GiB for extended memory variants (''M'' suffix) |
** UP to DDR4-2666 MT/s | ** UP to DDR4-2666 MT/s | ||
** [[ECC]] support | ** [[ECC]] support |
Facts about "Skylake SP - Cores - Intel"
chipset | Lewisburg + |
designer | Intel + |
first announced | May 4, 2017 + |
first launched | July 11, 2017 + |
instance of | core + |
isa | x86-64 + |
main image | + and + |
main image caption | Skylake SP, with HFI + |
manufacturer | Intel + |
microarchitecture | Skylake (server) + |
name | Skylake SP + |
package | FCLGA-3647 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | Socket P + and LGA-3647 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |