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Latest revision | Your text | ||
Line 33: | Line 33: | ||
** 8-32 GiB | ** 8-32 GiB | ||
* 16x PCIe | * 16x PCIe | ||
− | * [[ | + | * [[2 cores|2]]-[[4 cores|4]] |
* '''ISA:''' Everything up to AVX (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX) | * '''ISA:''' Everything up to AVX (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX) | ||
** Note that {{intel|Pentium (2009)|Pentium}} and {{intel|Celeron}} models only support up to {{x86|SSE4.2}} | ** Note that {{intel|Pentium (2009)|Pentium}} and {{intel|Celeron}} models only support up to {{x86|SSE4.2}} |
Facts about "Sandy Bridge M - Cores - Intel"
chipset | Cougar Point + |
designer | Intel + |
first announced | December 30, 2010 + |
first launched | January 5, 2011 + |
instance of | core + |
isa | x86-64 + |
isa family | x86 + |
manufacturer | Intel + |
microarchitecture | Sandy Bridge + |
name | Sandy Bridge M + |
process | 32 nm (0.032 μm, 3.2e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |