From WikiChip
Editing intel/cores/kaby lake h

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Latest revision Your text
Line 29: Line 29:
  
 
== Overview ==
 
== Overview ==
Kaby Lake H based processors are a 2-chip solution - the [[microprocessor]] and the [[chipset]]. Kaby Lake H are {{intel|BGA-1440|Socket BGA-1440}} and use {{intel|Union Point}} chipset ({{intel|Platform Controller Hub|HUB}}) but they may also use previous generation ({{intel|Skylake H|l=core}}) {{intel|Sunrise Point}} via a firmware upgrade. The microprocessor is connected to the chipset via 4 of the chip's 20 PCIe lanes using Intel's proprietary {{intel|Direct Media Interface}} 3.0 (DMI 3.0), allowing for 8 GT/s transfer rate per lane.
+
Kaby Lake H based processors are a 2-chip solution - the [[microprocessor]] and the [[chipset]]. Kaby Lake H are {{intel|socket BGA-1440}} and use {{intel|Union Point}} chipset ({{intel|Platform Controller Hub|HUB}}) but they may also use previous generation ({{intel|Skylake H|l=core}}) {{intel|Sunrise Point}} via a firmware upgrade. The microprocessor is connected to the chipset via 4 of the chip's 20 PCIe lanes using Intel's proprietary {{intel|Direct Media Interface}} 3.0 (DMI 3.0), allowing for 8 GT/s transfer rate per lane.
  
 
=== Common Features ===
 
=== Common Features ===

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)
designerIntel +
first announcedJanuary 3, 2017 +
first launchedJanuary 3, 2017 +
instance ofcore +
isax86-64 +
isa familyx86 +
main imageFile:kaby lake h (front).png + and File:kaby lake h (back).png +
manufacturerIntel +
microarchitectureKaby Lake +
nameKaby Lake H +
process14 nm (0.014 μm, 1.4e-5 mm) +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +