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=== Graphics ===
 
=== Graphics ===
Those processors are unique in the fact that this is the first time Intel has integrated a discrete graphics processor into the same package as the microprocessor. This is also the first time they are using a competitor's graphics processor. Those parts incorporate an [[AMD]] [[GPU]] based on the {{amd|Vega|l=arch}} microarchitecture and incorporate their own 4 GiB of [[high-bandwidth memory]] 2 (HBM2). The HBM solution is connected to the graphics processor using Intel's [[EMIB]], a high-speed in-package interconnect solution.
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Those processors are unique in the fact that this is the first time Intel has integrated a discrete graphics processor into the same package as the microprocessor. This is also the first time they are using a competitor graphics processor. Those parts incorporate an [[AMD]] [[GPU]] based on the {{amd|Vega|l=arch}} microarchitecture and incorporate their own 4 GiB of [[high-bandwidth memory]] 2 (HBM2). The HBM solution is connected to the graphics processor using Intel's [[EMIB]], a high-speed in-package interconnect solution.
  
 
The CPU itself is connected to the GPU using 8 of the other PCIe lanes, leaving the 8 remaining lanes for other peripherals to communicate with the CPU directly.
 
The CPU itself is connected to the GPU using 8 of the other PCIe lanes, leaving the 8 remaining lanes for other peripherals to communicate with the CPU directly.
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[[File:kaby lake g with amd radeon package.png|600px]]
 
[[File:kaby lake g with amd radeon package.png|600px]]
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=== Common Features ===
 
=== Common Features ===

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designerIntel + and AMD +
first announcedNovember 6, 2017 +
first launchedJanuary 7, 2018 +
instance ofcore +
isax86-64 +
isa familyx86 +
main imageFile:kaby lake g (front).png +
main image captionPackage front +
manufacturerIntel + and GlobalFoundries +
microarchitectureKaby Lake +
nameKaby Lake G +
process14 nm (0.014 μm, 1.4e-5 mm) +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +