Editing intel/cores/hewitt lake

{{intel title|Hewitt Lake|core}}
{{core
|name=Hewitt Lake
|image=hewitt lake (front).png
|developer=Intel
|manufacturer=Intel
|first announced=February 25, 2019
|first launched=April 2, 2019
|isa=x86-64
|isa family=x86
|microarch=Broadwell (Server)
|word=64 bit
|proc=14 nm
|tech=CMOS
|predecessor=Broadwell DE
|predecessor link=intel/cores/broadwell de
}}
'''Hewitt Lake''' ('''HWL''') is codename [[Intel]]'s single-chip dense low-power processors platform based on the {{intel|Broadwell (server)|Broadwell|l=arch}} microarchitecture, serving as a successor to {{\\|Broadwell DE}}. Hewitt Lake are aimed at lower power IoT, networking, and dense [[edge computing]].

Hewitt Lake parts are branded as [[Intel]] {{intel|xeon d#D-1600 Series .28Broadwell.29|Xeon D-1600}} series processors.

== Overview ==
All processors are a single-socket {{intel|BGA-1667}} package, manufacturing on Intel's [[14 nm process]] based on the {{intel|Broadwell (server)|Broadwell|l=arch}} microarchitecture. Hewitt Lake processors are a single-chip solution consisting of just the processor chip itself since they incorporate the chipset along with the microprocessor die in the same package.

=== Common Features ===
All models have all the following features in common:

* '''TDP:''' 27-65 W
* '''Mem:''' 128 GiB dual-channel DDR4 ECC memory up to 2133/2400 MT/s. (128 GiB @ [[RDIMM]] 32 GiB/DIMM, 64 GiB @ UDIMM/SODIMM 16 GiB/DIMM
* '''I/O:''' 32 PCIe 3/2 lanes (x24 Gen3 + x8 Gen2)
* '''ISA:''' Everything up to {{x86|AVX2}} ({{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}})
* '''Features:''' {{intel|SpeedStep}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Secure Key}}, and {{intel|OS Guard}}

Hewitt Lake SKUs are organized into three groups:

* '''Edge Server and Cloud SUKs'''
* '''Integrated QuickAssist Technology''' - SKUs with Intel's {{intel|QuickAssist}} technology enabled. QAT allows for up to 100 Gps of encryption and decryption [[hardware acceleration|acceleration]].

Additionally, SKUs are suffixed with '''N''' or combination of multiple of those options:

* '''N''' - Integrated Ethernet and Intel's {{intel|QuickAssist}} technology


== Hewitt Lake Processors==
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           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc4 tc5 tc11">
{{comp table header|main|11:List of Hewitt Lake-based Processors}}
{{comp table header|cols|Launched|Price|Cores|Threads|TDP|L2|L3|%Frequency|%Turbo|QAT}}
{{comp table header|lsep|11:Edge Server and Cloud SKUs}}
{{#ask: [[Category:microprocessor models by intel]] [[core name::Hewitt Lake]] [[model number ::!~*N]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?core count
 |?thread count
 |?tdp
 |?l2$ size
 |?l3$ size
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?has integrated intel quickassist technology
 |format=template
 |template=proc table 3
 |userparam=12:12
 |sort=model number
 |mainlabel=-
}}
{{comp table header|lsep|11:Network Edge and Storage SKUs}}
{{#ask: [[Category:microprocessor models by intel]] [[core name::Hewitt Lake]] [[model number ::~*N]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?core count
 |?thread count
 |?tdp
 |?l2$ size
 |?l3$ size
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?has integrated intel quickassist technology
 |format=template
 |template=proc table 3
 |userparam=12:12
 |sort=model number
 |mainlabel=-
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[core name::Hewitt Lake]]}}
</table>
{{comp table end}}

=== SKU Comparison ===
Below are a number of SKU comparison graphs based on their specifications.

<div style="float: left; margin: 10px">
{{#ask: [[Category:microprocessor models by intel]] [[core name::Hewitt Lake]]
 |?core count
 |?base frequency
 |charttitle=Cores vs. Frequency
 |numbersaxislabel=Frequency (MHz)
 |labelaxislabel=Core Count
 |height=400
 |width=400
 |theme=vector
 |group=property
 |grouplabel=subject
 |charttype=scatter
 |format=jqplotseries
 |mainlabel=-
}}
</div>

<div style="float: left; margin: 10px">
{{#ask: [[Category:microprocessor models by intel]] [[core name::Hewitt Lake]]
 |?core count
 |?turbo frequency (1 core)
 |charttitle=Cores vs. Turbo Frequency
 |numbersaxislabel=Frequency (MHz)
 |labelaxislabel=Core Count
 |height=400
 |width=400
 |theme=vector
 |group=property
 |grouplabel=subject
 |charttype=scatter
 |format=jqplotseries
 |mainlabel=-
}}
</div>

<div style="float: left; margin: 10px">
{{#ask: [[Category:microprocessor models by intel]] [[core name::Hewitt Lake]]
 |?core count
 |?tdp
 |charttitle=Cores vs. TDP
 |numbersaxislabel=TDP (W)
 |labelaxislabel=Core Count
 |height=400
 |width=400
 |theme=vector
 |group=property
 |grouplabel=subject
 |charttype=scatter
 |format=jqplotseries
 |mainlabel=-
}}
</div>

<div style="float: left; margin: 10px">
{{#ask: [[Category:microprocessor models by intel]] [[core name::Hewitt Lake]]
 |?turbo frequency (1 core)
 |?tdp
 |charttitle=Frequency vs. TDP
 |numbersaxislabel=TDP (W)
 |labelaxislabel=Frequency (MHz)
 |height=400
 |width=400
 |theme=vector
 |group=property
 |grouplabel=subject
 |charttype=scatter
 |format=jqplotseries
 |mainlabel=-
}}
</div>

<div style="float: left; margin: 10px">
{{#ask: [[Category:microprocessor models by intel]] [[core name::Hewitt Lake]]
 |?core count
 |?release price
 |charttitle=Cores vs. Price
 |numbersaxislabel=Price ($)
 |labelaxislabel=Core Count
 |height=400
 |width=400
 |theme=vector
 |group=property
 |grouplabel=subject
 |charttype=scatter
 |format=jqplotseries
 |mainlabel=-
}}
</div>

{{clear}}

== See also ==
{{intel broadwell core see also}}
designer	Intel +
first announced	February 25, 2019 +
first launched	April 2, 2019 +
instance of	core +
isa	x86-64 +
isa family	x86 +
main image	+
manufacturer	Intel +
microarchitecture	Broadwell (Server) +
name	Hewitt Lake +
process	14 nm (0.014 μm, 1.4e-5 mm) +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +