Editing intel/cores/cascade lake r

{{intel title|Cascade Lake R|core}}
{{core
|name=Cascade Lake R
|image=cascade lake sp (front).png
|developer=Intel
|manufacturer=Intel
|first announced=February 24, 2020
|first launched=February 24, 2020
|isa=x86-64
|isa family=x86
|microarch=Cascade Lake
|platform=Purley
|chipset=Lewisburg
|word=64 bit
|proc=14 nm
|tech=CMOS
|package name 1=intel,fclga_3647
|predecessor=Cascade Lake SP
|predecessor link=intel/cores/cascade lake sp
|successor=Ice Lake SP
|successor link=intel/cores/ice lake sp
}}
'''Cascade Lake R''' ('''{{intel|Cascade Lake|l=arch}} Scalable Performance Refresh''') is code name for Intel's series of server [[multiprocessors]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture as part of the {{intel|Purley|l=platform}} platform serving as mid-cycle refresh to {{intel|Cascade Lake SP|l=core}}. Cascade Lake R only targets mainstream entry and mid-range servers and therefore only support up to 2-way multiprocessing. As with {{\\|Cascade Lake SP}}, these chips also support up to [[28 cores]], incorporate {{x86|AVX512-VNNI|AVX512}} [[x86]] {{x86|extension}} for neural network / deep learning workloads, and introduces [[persistent memory]] support. Cascade Lake R-based chips are manufactured on an enhanced [[14 nm process]] and utilize the {{intel|Lewisburg|l=chipset}} chipset.

Cascade Lake R-based models are branded as the 2nd-generation {{intel|Xeon Bronze}}, {{intel|Xeon Silver}}, and {{intel|Xeon Gold}} [[processor families]].

== Overview ==
Cascade Lake R processors are based on Intel's {{intel|Cascade Lake|l=arch}} microarchitecture intended to enhance the original {{\\|Cascade Lake SP}} lineup. These processors introduce a significant price cut compared to original SKUs or additional cores and the higher frequency at comparable price. The intended purpose of this release is to elevate the performance-per-dollar for entry-level and mid-range server processors.

As with {{\\|Skylake SP}}, Cascade Lake SP processors utilize the new {{intel|FCLGA-3647}} package (which makes use of "Socket P"). Those use the {{intel|Lewisburg}} chipset ({{intel|Platform Controller Hub|HUB}}) via 4 PCIe3 lanes using Intel's proprietary {{intel|Direct Media Interface}} 3.0 (DMI 3.0), allowing for 8 GT/s transfer rate per lane. When in multi-socket configuration, the microprocessor is connected to the other processors via the {{intel|Ultra Path Interconnect}} (UPI) links which Intel introduced with Skylake SP as well, replacing and obsoleting the older {{intel|QuickPath Interconnect}} (QPI) operating. Depending on the model, there may be either two or three UPI links inter-linking each socket (for more details see {{intel|cascade lake#Scalability|Cascade Lake § Scalability|l=arch}}).

=== Common Features ===
All Cascade Lake R processors have the following:

* Hexa-channel memory
** 1 TiB, 2 TiB medium memory support variants (''M'' suffix), and 4.5 TiB for extended memory variants (''L'' suffix)
** UP to DDR4-2933 MT/s
** [[ECC]] support
* '''TDP:''' 85 W to 205 W
* '''PCIe:''' x48 Lanes of PCIe Gen 3
* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, AVX512DQ, AVX512VL, AVX512VNNI)
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).
** Silver and up also have {{intel|Hyper-Threading}} and {{intel|Turbo Boost}}
** Gold and up also have Node Controller Support and offer Integrated Omni-Path Fabric Interface options

{{clear}}

=== Naming Scheme ===
Cascade Lake SKUs follow the following naming scheme.

:[[File:cascade lake naming scheme.svg|600px]]

Where,

* "''F''" suffix integrates the {{intel|Omni-Path}} Host Fabric Interface (HFI) die on-package
* "''L''" suffix indicates the SKU is a large memory (4.5 TiB) tier SKU
* "''M''" suffix indicates the SKU is a medium memory (2 TiB) tier SKU
* "''N''" suffix indicates the SKU is a networking-specialized model
* "''S''" suffix indicates the SKU is a search application-specialized model
* "''T''" suffix indicates that SKU has an extended lifetime (10 year use) guarantees and [[NEBS]]-friendly packing specification
* "''V''" suffix indicates the SKU targets the VM density value market 
* "''Y''" suffix indicates the SKU has {{intel|Speed Select Technology}} (SST)
* "''U''" suffix indicates the SKU is a single-socket model (even if part of the [[Xeon Gold]] family that normally supports up two 4-way [[SMP]])
* "''R''" suffix indicates the SKU is a dual-socket model (even if part of the [[Xeon Gold]] family that normally supports up two 4-way [[SMP]])

== Cascade Lake R Processors ==
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{{comp table start}}
<table class="comptable sortable tc5 tc6 tc14">
{{comp table header|main|12:List of Cascade Lake R-based Processors}}
{{comp table header|main|8:Main Processor|1:Cache|2:Memory}}
{{comp table header|cols|Family|Price|Launched|Cores|Threads|Frequency|Max Turbo|%TDP|L3$|Mem Type|Max Mem}}
{{comp table header|lsep|25:[[Multiprocessors]] (2-way)}}
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Cascade Lake R]] [[max cpu count::2]]
 |?full page name
 |?model number
 |?microprocessor family
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?tdp
 |?l3$ size
 |?supported memory type
 |?max memory#TiB
 |format=template
 |template=proc table 3
 |userparam=13
 |mainlabel=-
 |limit=75
 |valuesep=,
 |sort=model number
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Cascade Lake R]]}}
</table>
{{comp table end}}

=== SKU Comparison ===
Below are a number of SKU comparison graphs based on their specifications.

<div style="float: left; margin: 10px">
{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake R]]
 |?core count
 |?base frequency
 |charttitle=Cores vs. Base Frequency
 |numbersaxislabel=Frequency (MHz)
 |labelaxislabel=Core Count
 |height=400
 |width=400
 |theme=vector
 |group=property
 |grouplabel=subject
 |charttype=scatter
 |format=jqplotseries
 |mainlabel=-
}}
</div>

<div style="float: left; margin: 10px">
{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake R]]
 |?core count
 |?turbo frequency (1 core)
 |charttitle=Cores vs. Turbo Frequency
 |numbersaxislabel=Frequency (MHz)
 |labelaxislabel=Core Count
 |height=400
 |width=400
 |theme=vector
 |group=property
 |grouplabel=subject
 |charttype=scatter
 |format=jqplotseries
 |mainlabel=-
}}
</div>

<div style="float: left; margin: 10px">
{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake R]]
 |?core count
 |?tdp
 |charttitle=Cores vs. TDP
 |numbersaxislabel=TDP (W)
 |labelaxislabel=Core Count
 |height=400
 |width=400
 |theme=vector
 |group=property
 |grouplabel=subject
 |charttype=scatter
 |format=jqplotseries
 |mainlabel=-
}}
</div>

<div style="float: left; margin: 10px">
{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake R]]
 |?turbo frequency (1 core)
 |?tdp
 |charttitle=Frequency vs. TDP
 |numbersaxislabel=TDP (W)
 |labelaxislabel=Frequency (MHz)
 |height=400
 |width=400
 |theme=vector
 |group=property
 |grouplabel=subject
 |charttype=scatter
 |format=jqplotseries
 |mainlabel=-
}}
</div>

{{clear}}

== See also ==
{{intel cascade lake core see also}}
chipset	Lewisburg +
designer	Intel +
first announced	February 24, 2020 +
first launched	February 24, 2020 +
instance of	core +
isa	x86-64 +
isa family	x86 +
main image	+
manufacturer	Intel +
microarchitecture	Cascade Lake +
name	Cascade Lake R +
package	FCLGA-3647 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
socket	Socket P + and LGA-3647 +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +