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Difference between revisions of "intel/cores/cascade lake ap"
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{{core
 
{{core
 
|name=Cascade Lake AP
 
|name=Cascade Lake AP
|no image=Yes
+
|image=cascade lake ap (front).png
 
|developer=Intel
 
|developer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
 
|isa=x86-64
 
|isa=x86-64
 
|microarch=Cascade Lake
 
|microarch=Cascade Lake
|platform=Purley
+
|platform=Walker Pass
|chipset=Lewisburg
 
 
|word=64 bit
 
|word=64 bit
 
|proc=14 nm
 
|proc=14 nm
 
|tech=CMOS
 
|tech=CMOS
|package name 1=intel,bga_5903
+
|package name 1=intel,fcbga_5903
 
}}
 
}}
'''Cascade Lake AP''' is a planned series of server [[multiprocessors]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture as part of the {{intel|Purley|l=platform}} platform.
+
'''Cascade Lake AP''' ('''CLX-AP''', '''Cascade Lake Advanced Performance''') is code name for a series of high core-count multi-chip packaged server [[multiprocessors]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture part of the {{intel|Walker Pass|l=platform}} platform.
  
 +
Cascade Lake AP-based processors are branded as {{intel|Xeon Platinum}} 9200-series.
  
{{future information}}
+
== Overview ==
 +
Cascade Lake AP comprise of two {{intel|Cascade Lake|l=arch}} dies packaged together a single BGA-5903 substrate. Those processors support up to 56 cores, 112 threads, and up to 12 DDR4 channels.
 +
 
 +
Cascade Lake AP processors cannot be purchased individually. Instead, they can only be bought as part of the S9200WK compute module (essentially a complete system designed by Intel).
 +
 
 +
=== Common Features ===
 +
* 12-channel memory
 +
** UP to DDR4-2933 MT/s
 +
** ECC support
 +
* '''TDP:''' 250 W to 400 W
 +
* '''PCIe:''' x40 Lanes of PCIe Gen 3 (limited by the S9200WK module, actual models support more lanes but are not sold independently)
 +
* '''ISA:''' Everything up to {{x86|AVX-512}} (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, {{x86|AVX512DQ}}, {{x86|AVX512VL}}, {{x86|AVX512VNNI}})
 +
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}
 +
 
 +
{{clear}}
 +
 
 +
== Cascade Lake AP Processors==
 +
<!-- NOTE:
 +
          This table is generated automatically from the data in the actual articles.
 +
          If a microprocessor is missing from the list, an appropriate article for it needs to be
 +
          created and tagged accordingly.
 +
 
 +
          Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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-->
 +
{{comp table start}}
 +
<table class="comptable sortable tc3 tc4 tc5 tc6 tc7 tc8">
 +
{{comp table header|main|11:List of Cascade Lake AP-based Processors}}
 +
{{comp table header|cols|Launched|Cores|Threads|TDP|L2|L3|%Frequency|%Turbo}}
 +
{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake AP]]
 +
|?full page name
 +
|?model number
 +
|?first launched
 +
|?core count
 +
|?thread count
 +
|?tdp
 +
|?l2$ size
 +
|?l3$ size
 +
|?base frequency#GHz
 +
|?turbo frequency (1 core)#GHz
 +
|format=template
 +
|template=proc table 3
 +
|userparam=10
 +
|sort=model number
 +
|mainlabel=-
 +
}}
 +
{{comp table count|ask=[[Category:microprocessor models by intel]] [[core name::Cascade Lake AP]]}}
 +
</table>
 +
{{comp table end}}
 +
 
 +
=== SKU Comparison ===
 +
Below are a number of SKU comparison graphs based on their specifications.
 +
 
 +
<div style="float: left; margin: 10px">
 +
{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake AP]]
 +
|?core count
 +
|?base frequency
 +
|charttitle=Cores vs. Base Frequency
 +
|numbersaxislabel=Frequency (MHz)
 +
|labelaxislabel=Core Count
 +
|height=400
 +
|width=400
 +
|theme=vector
 +
|group=property
 +
|grouplabel=subject
 +
|charttype=scatter
 +
|format=jqplotseries
 +
|mainlabel=-
 +
}}
 +
</div>
 +
 
 +
<div style="float: left; margin: 10px">
 +
{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake AP]]
 +
|?core count
 +
|?turbo frequency (1 core)
 +
|charttitle=Cores vs. Turbo Frequency
 +
|numbersaxislabel=Frequency (MHz)
 +
|labelaxislabel=Core Count
 +
|height=400
 +
|width=400
 +
|theme=vector
 +
|group=property
 +
|grouplabel=subject
 +
|charttype=scatter
 +
|format=jqplotseries
 +
|mainlabel=-
 +
}}
 +
</div>
 +
 
 +
<div style="float: left; margin: 10px">
 +
{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake AP]]
 +
|?core count
 +
|?tdp
 +
|charttitle=Cores vs. TDP
 +
|numbersaxislabel=TDP (W)
 +
|labelaxislabel=Core Count
 +
|height=400
 +
|width=400
 +
|theme=vector
 +
|group=property
 +
|grouplabel=subject
 +
|charttype=scatter
 +
|format=jqplotseries
 +
|mainlabel=-
 +
}}
 +
</div>
 +
 
 +
<div style="float: left; margin: 10px">
 +
{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake AP]]
 +
|?turbo frequency (1 core)
 +
|?tdp
 +
|charttitle=Frequency vs. TDP
 +
|numbersaxislabel=TDP (W)
 +
|labelaxislabel=Frequency (MHz)
 +
|height=400
 +
|width=400
 +
|theme=vector
 +
|group=property
 +
|grouplabel=subject
 +
|charttype=scatter
 +
|format=jqplotseries
 +
|mainlabel=-
 +
}}
 +
</div>
 +
 
 +
{{clear}}
  
 
== See also ==
 
== See also ==
 
{{intel cascade lake core see also}}
 
{{intel cascade lake core see also}}

Revision as of 19:23, 13 July 2019

Edit Values
Cascade Lake AP
cascade lake ap (front).png
General Info
DesignerIntel
ManufacturerIntel
Microarchitecture
ISAx86-64
MicroarchitectureCascade Lake
PlatformWalker Pass
Word Size
8 octets
16 nibbles
64 bit
Process14 nm
0.014 μm
1.4e-5 mm
TechnologyCMOS
Packaging
PackageFCBGA-5903 (BGA)
Pitch0.99 mm
Contacts5903

Cascade Lake AP (CLX-AP, Cascade Lake Advanced Performance) is code name for a series of high core-count multi-chip packaged server multiprocessors based on the Cascade Lake microarchitecture part of the Walker Pass platform.

Cascade Lake AP-based processors are branded as Xeon Platinum 9200-series.

Overview

Cascade Lake AP comprise of two Cascade Lake dies packaged together a single BGA-5903 substrate. Those processors support up to 56 cores, 112 threads, and up to 12 DDR4 channels.

Cascade Lake AP processors cannot be purchased individually. Instead, they can only be bought as part of the S9200WK compute module (essentially a complete system designed by Intel).

Common Features

  • 12-channel memory
    • UP to DDR4-2933 MT/s
    • ECC support
  • TDP: 250 W to 400 W
  • PCIe: x40 Lanes of PCIe Gen 3 (limited by the S9200WK module, actual models support more lanes but are not sold independently)
  • ISA: Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, AVX512DQ, AVX512VL, AVX512VNNI)
  • Features: Speed Shift, vPro, VT-x, TSX, TXT

Cascade Lake AP Processors

 List of Cascade Lake AP-based Processors
ModelLaunchedCoresThreadsTDPL2L3FrequencyTurbo
92212 April 20193264250 W
250,000 mW
0.335 hp
0.25 kW
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
71.5 MiB
73,216 KiB
74,973,184 B
0.0698 GiB
2.1 GHz
2,100 MHz
2,100,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
92222 April 20193264250 W
250,000 mW
0.335 hp
0.25 kW
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
71.5 MiB
73,216 KiB
74,973,184 B
0.0698 GiB
2.3 GHz
2,300 MHz
2,300,000 kHz
3.7 GHz
3,700 MHz
3,700,000 kHz
92422 April 20194896350 W
350,000 mW
0.469 hp
0.35 kW
48 MiB
49,152 KiB
50,331,648 B
0.0469 GiB
71.5 MiB
73,216 KiB
74,973,184 B
0.0698 GiB
2.3 GHz
2,300 MHz
2,300,000 kHz
3.8 GHz
3,800 MHz
3,800,000 kHz
92822 April 201956112400 W
400,000 mW
0.536 hp
0.4 kW
56 MiB
57,344 KiB
58,720,256 B
0.0547 GiB
77 MiB
78,848 KiB
80,740,352 B
0.0752 GiB
2.6 GHz
2,600 MHz
2,600,000 kHz
3.8 GHz
3,800 MHz
3,800,000 kHz
Count: 4

SKU Comparison

Below are a number of SKU comparison graphs based on their specifications.

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See also

arrow up 1.svgPower/Performance

designerIntel +
instance ofcore +
isax86-64 +
main imageFile:cascade lake ap (front).png +
manufacturerIntel +
microarchitectureCascade Lake +
nameCascade Lake AP +
packageFCBGA-5903 +
platformWalker Pass +
process14 nm (0.014 μm, 1.4e-5 mm) +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +