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=== Skylake Refresh ===
 
=== Skylake Refresh ===
 
{{see also|intel/cores/skylake x refresh|l1=Skylake X Refresh}}
 
{{see also|intel/cores/skylake x refresh|l1=Skylake X Refresh}}
In late 2018 Intel {{intel|Skylake X Refresh|l=core|refreshed}} the entire {{intel|Skylake X|l=core}} lineup. In addition to the higher clock frequencies achieved as a result of utilizing their mature [[14 nm process]], those processors also makes use of [[solder thermal interface material]] instead of a paste, increasing the thermal conductivity and improving the available [[overclocking]] headroom. The refreshed lineup got rid of the [[hexa-core]] part and eliminates the PCIe lanes-based segmentation, providing x44 PCIe lanes on all models. Additionally, all models under [[12 cores]] come with a larger [[L3 cache]]. Most of the low All models have the following common features:
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In late 2018 Intel {{intel|Skylake X Refresh|l=core|refreshed}} the entire {{intel|Skylake X|l=core}} lineup. In addition to the higher clock frequencies achieved as a result of utilizing their mature [[14 nm process]], those processors also utilize a [[solder thermal interface material]] instead of a paste, increasing the thermal conductivity and improving the avilable [[overclocking]] headroom. The refreshed lineup got rid of the [[hexa-core]] part and eliminates the PCIe lanes-based segmentation, providing x44 PCIe lanes on all models. Additionally, all models under [[12 cores]] come with a larger [[L3 cache]]. Most of the low All models have the following common features:
  
 
* '''TDP:''' 165 W
 
* '''TDP:''' 165 W

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Facts about "Core X - Intel"
designerIntel +
first announcedMay 30, 2017 +
full page nameintel/core x +
instance ofmicroprocessor family +
main designerIntel +
manufacturerIntel +
microarchitectureSkylake + and Kaby Lake +
nameCore X +
packageFCLGA-2066 +
process14 nm (0.014 μm, 1.4e-5 mm) +
socketSocket R +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +