Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/core m/m3-7y30"
(updated specs) |
|||
| Line 9: | Line 9: | ||
| manufacturer = Intel | | manufacturer = Intel | ||
| model number = M3-7Y30 | | model number = M3-7Y30 | ||
| − | | part number = | + | | part number = HE8067702739824 |
| + | | part number 1 = | ||
| + | | part number 2 = | ||
| + | | s-spec = SR2ZY | ||
| + | | s-spec 2 = SR347 | ||
| market = Mobile | | market = Mobile | ||
| first announced = August 30, 2016 | | first announced = August 30, 2016 | ||
| Line 18: | Line 22: | ||
| family = Core M3 | | family = Core M3 | ||
| − | | series = | + | | series = m3-7Y |
| locked = Yes | | locked = Yes | ||
| − | | frequency = | + | | frequency = 1,000 MHz |
| turbo frequency = Yes | | turbo frequency = Yes | ||
| − | | turbo frequency1 = | + | | turbo frequency1 = 2,600 MHz |
| turbo frequency2 = | | turbo frequency2 = | ||
| − | | bus type = | + | | turbo frequency3 = |
| + | | turbo frequency4 = | ||
| + | | bus type = OPI | ||
| bus speed = | | bus speed = | ||
| − | | bus rate = | + | | bus rate = 4 GT/s |
| + | | bus links = | ||
| clock multiplier = 10 | | clock multiplier = 10 | ||
| − | |||
| − | |||
| − | |||
| cpuid = | | cpuid = | ||
| Line 36: | Line 40: | ||
| isa = x86-64 | | isa = x86-64 | ||
| microarch = Kaby Lake | | microarch = Kaby Lake | ||
| − | | platform = | + | | platform = Kaby Lake |
| − | | chipset = | + | | chipset = Sunrise Point |
| + | | chipset 2 = Union Point | ||
| core name = Kaby Lake Y | | core name = Kaby Lake Y | ||
| − | | core family = | + | | core family = 6 |
| − | | core model = | + | | core model = 142 |
| − | | core stepping = | + | | core stepping = H0 |
| + | | core stepping 2 = | ||
| process = 14 nm | | process = 14 nm | ||
| transistors = | | transistors = | ||
| technology = CMOS | | technology = CMOS | ||
| − | | die | + | | die area = |
| + | | die width = | ||
| + | | die length = | ||
| word size = 64 bit | | word size = 64 bit | ||
| core count = 2 | | core count = 2 | ||
| thread count = 4 | | thread count = 4 | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 16 | + | | max memory = 16 GiB |
| electrical = Yes | | electrical = Yes | ||
| − | | v core | + | | v core min = 0.55 V |
| − | | v core | + | | v core max = 1.52 V |
| sdp = | | sdp = | ||
| tdp = 4.5 W | | tdp = 4.5 W | ||
| − | | ctdp down = 3. | + | | tdp typical = |
| + | | ctdp down = 3.75 W | ||
| ctdp down frequency = 600 MHz | | ctdp down frequency = 600 MHz | ||
| ctdp up = 7 W | | ctdp up = 7 W | ||
| − | | ctdp up frequency = | + | | ctdp up frequency = 1,600 MHz |
| − | |||
| − | |||
| tjunc min = 0 °C | | tjunc min = 0 °C | ||
| tjunc max = 100 °C | | tjunc max = 100 °C | ||
| tcase min = | | tcase min = | ||
| tcase max = | | tcase max = | ||
| − | | tstorage min = | + | | tstorage min = -25 °C |
| − | | tstorage max = | + | | tstorage max = 125 °C |
| + | | tambient min = | ||
| + | | tambient max = | ||
| packaging = Yes | | packaging = Yes | ||
| − | | package | + | | package 0 = FCBGA-1515 |
| − | | package type | + | | package 0 type = FCBGA |
| − | | package pitch | + | | package 0 pins = 1515 |
| − | | package | + | | package 0 pitch = 0.4 mm |
| − | | socket | + | | package 0 width = 20 mm |
| − | | socket type | + | | package 0 length = 16.5 mm |
| + | | package 0 height = | ||
| + | | socket 0 = BGA-1515 | ||
| + | | socket 0 type = BGA | ||
}} | }} | ||
The '''Core M3-7Y30''' is an ultra-low power dual-core {{arch|64}} [[x86]] microprocessor introduced by [[Intel]] in mid-2016. This MPU operates at 1 GHz with a max turbo frequency of 2.6 GHz. This chip, which is manufactured in [[14 nm process]] based on the {{intel|Kaby Lake}} microarchitecture and incorporates Intel's {{intel|HD Graphics 615}} GPU clocked at 300 MHz with turbo frequency of 900 MHz. | The '''Core M3-7Y30''' is an ultra-low power dual-core {{arch|64}} [[x86]] microprocessor introduced by [[Intel]] in mid-2016. This MPU operates at 1 GHz with a max turbo frequency of 2.6 GHz. This chip, which is manufactured in [[14 nm process]] based on the {{intel|Kaby Lake}} microarchitecture and incorporates Intel's {{intel|HD Graphics 615}} GPU clocked at 300 MHz with turbo frequency of 900 MHz. | ||
Revision as of 01:53, 7 January 2017
Template:mpu The Core M3-7Y30 is an ultra-low power dual-core 64-bit x86 microprocessor introduced by Intel in mid-2016. This MPU operates at 1 GHz with a max turbo frequency of 2.6 GHz. This chip, which is manufactured in 14 nm process based on the Kaby Lake microarchitecture and incorporates Intel's HD Graphics 615 GPU clocked at 300 MHz with turbo frequency of 900 MHz.
Cache
- Main article: Kaby Lake § Cache
| Cache Info [Edit Values] | ||
| L3$ | 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB |
2x2 MiB (shared LLC) |
Graphics
| Integrated Graphic Information | |
| GPU | Intel HD Graphics 615 |
| Device ID | 0x591E |
| Execution Units | 24 |
| Displays | 3 |
| Frequency | 300 MHz 0.3 GHz
300,000 KHz |
| Max frequency | 900 MHz 0.9 GHz
900,000 KHz |
| Max memory | 16 GB "GB" is not declared as a valid unit of measurement for this property.
|
| Output | DisplayPort, Embedded DisplayPort, HDMI, DVI |
| DirectX | 12 |
| OpenGL | 4.4 |
| OpenCL | 2.0 |
| HDMI | 1.4a |
| DP | 1.2 |
| eDP | 1.3 |
| Max HDMI Res | 4096x2304 @24 Hz |
| Max DP Res | 3840x2160 @60 Hz, 2880x1800 @60 Hz |
| Max eDP Res | 3840x2160 @60 Hz, 3840x2160 @60 Hz |
| Intel Quick Sync Video | |
| Intel InTru 3D | |
| Intel Insider | |
| Intel WiDi (Wireless Display) | |
| Intel Clear Video | |
Memory controller
| Integrated Memory Controller | |
| Type | LPDDR3-1866, LPDDR3-1600 |
| Controllers | 1 |
| Channels | 2 |
| ECC Support | No |
| Max bandwidth | 29.8 GB/s |
| Max memory | 16 GB |
Expansions
Features
Facts about "Core M3-7Y30 - Intel"
| device id | 0x591E + |
| has feature | integrated gpu + |
| integrated gpu | Intel HD Graphics 615 + |
| integrated gpu base frequency | 300 MHz (0.3 GHz, 300,000 KHz) + |
| integrated gpu max frequency | 900 MHz (0.9 GHz, 900,000 KHz) + |
| l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
