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Difference between revisions of "intel/core i7ee/i7-975"
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(Cache)
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{{main|intel/microarchitectures/nehalem#Memory_Hierarchy|l1=Nehalem's Cache}}
 
{{main|intel/microarchitectures/nehalem#Memory_Hierarchy|l1=Nehalem's Cache}}
 
{{cache info
 
{{cache info
|l1i cache=128 KB
+
|l1i cache=128 KiB
|l1i break=4x32 KB
+
|l1i break=4x32 KiB
 
|l1i desc=4-way set associative
 
|l1i desc=4-way set associative
 
|l1i extra=(per core; writeback/allocate)
 
|l1i extra=(per core; writeback/allocate)
|l1d cache=128 KB
+
|l1d cache=128 KiB
|l1d break=4x32 KB
+
|l1d break=4x32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
 
|l1d extra=(per core; writeback/allocate)
 
|l1d extra=(per core; writeback/allocate)
|l2 cache=1 MB
+
|l2 cache=1 MiB
|l2 break=4x256 KB
+
|l2 break=4x256 KiB
 
|l2 desc=8-way set associative
 
|l2 desc=8-way set associative
 
|l2 extra=(per core; writeback/allocate)
 
|l2 extra=(per core; writeback/allocate)

Revision as of 01:03, 21 September 2016

Template:mpu The Core i7-975 Extreme Edition is a 64-bit quad-core microprocessor introduced by Intel in mid-2009. The i7-975 along with the i7-965 became Intel's flagship desktop microprocessors for the Nehalem microarchitecture. This processor operates at 3.33 GHz with turbo frequency of up to 3.6 GHz for a single core. This chip supports up to 24 GB of memory and has a thermal design power of 130 W.

Cache

Main article: Nehalem's Cache
Cache Info [Edit Values]
L1I$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 4-way set associative (per core; writeback/allocate)
L1D$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core; writeback/allocate)
L2$ 1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
4x256 KiB 8-way set associative (per core; writeback/allocate)
L3$ 8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
16-way set associative (writeback/allocate)

Memory controller

Integrated Memory Controller
Type DDR3-800, DDR3-1066
Controllers 1
Channels 3
ECC Support No
Max bandwidth 25,600 MB/s
Max memory 24 GB

Graphics

This MPU has no integrated graphics processing unit.

Features

Template:mpu features

See also

l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description4-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description16-way set associative +
l3$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +