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Difference between revisions of "intel/core i7ee/i7-4960x"
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(Cache)
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{{main|intel/microarchitectures/ivy bridge#Memory_Hierarchy|l1=Ivy Bridge's Cache}}
 
{{main|intel/microarchitectures/ivy bridge#Memory_Hierarchy|l1=Ivy Bridge's Cache}}
 
{{cache info
 
{{cache info
|l1i cache=192 KB
+
|l1i cache=192 KiB
|l1i break=6x32 KB
+
|l1i break=6x32 KiB
 
|l1i desc=8-way set associative
 
|l1i desc=8-way set associative
 
|l1i extra=(per core)
 
|l1i extra=(per core)
|l1d cache=192 KB
+
|l1d cache=192 KiB
|l1d break=6x32 KB
+
|l1d break=6x32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
 
|l1d extra=(per core)
 
|l1d extra=(per core)
|l2 cache=1,536 KB
+
|l2 cache=1,536 KiB
|l2 break=6x256 KB
+
|l2 break=6x256 KiB
 
|l2 desc=8-way set associative
 
|l2 desc=8-way set associative
 
|l2 extra=(per core)
 
|l2 extra=(per core)

Revision as of 00:41, 21 September 2016

Template:mpu The Core i7-4960X Extreme Edition is a 64-bit hexa-core top-of-the-line MPU introduced by Intel for the enthusiasts market. The i7-4960X served as Intel's flagship microprocessor for the Ivy Bridge microarchitecture - it was superseded by the Haswell-based i7-5960X MPU. Operating at 3.6 GHz with turbo frequency of 4 GHz for a single core, this chip supports 64 GB of memory (DDR3) and has a TDP of 130 Watts.

Cache

Main article: Ivy Bridge's Cache
Cache Info [Edit Values]
L1I$ 192 KiB
196,608 B
0.188 MiB
6x32 KiB 8-way set associative (per core)
L1D$ 192 KiB
196,608 B
0.188 MiB
6x32 KiB 8-way set associative (per core)
L2$ 1,536 KiB
1.5 MiB
1,572,864 B
0.00146 GiB
6x256 KiB 8-way set associative (per core)
L3$ 15 MiB
15,360 KiB
15,728,640 B
0.0146 GiB
20-way set associative (shared)

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR3-1066, DDR3-1333, DDR3-1600, DDR3-1866
Controllers 1
Channels 4
ECC Support No
Max bandwidth 59.7 GB/s
Max memory 64 GB

Expansions

Template:mpu expansions

Features

Template:mpu features

Die Shot

  • 22 nm process
  • 1,860,000,000 transistors
  • 256.5 mm²
  • 15.0 mm x 17.1 mm
ivy bridge (hexa-core) die shot.png
ivy bridge (hexa-core) die shot (annotated).png

See also

l1d$ description8-way set associative +
l1d$ size192 KiB (196,608 B, 0.188 MiB) +
l1i$ description8-way set associative +
l1i$ size192 KiB (196,608 B, 0.188 MiB) +
l2$ description8-way set associative +
l2$ size1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) +
l3$ description20-way set associative +
l3$ size15 MiB (15,360 KiB, 15,728,640 B, 0.0146 GiB) +