From WikiChip
Difference between revisions of "intel/core i7ee/i7-4960x"
< intel‎ | core i7ee

m
Line 41: Line 41:
 
| core stepping      = S1
 
| core stepping      = S1
 
| process            = 22 nm
 
| process            = 22 nm
| transistors        =  
+
| transistors        = 1,860,000,000
 
| technology          = CMOS
 
| technology          = CMOS
| die size           =  
+
| die area           = 256.5 mm²
 +
| die width          = 15.0 mm
 +
| die length          = 17.1 mm
 
| word size          = 64 bit
 
| word size          = 64 bit
 
| core count          = 6
 
| core count          = 6
Line 158: Line 160:
 
| os guard    =  
 
| os guard    =  
 
}}
 
}}
 +
 +
== Die Shot ==
 +
* [[22 nm process]]
 +
* 1,860,000,000 transistors
 +
* 256.5 mm²
 +
* 15.0 mm x 17.1 mm
 +
 +
:[[File:ivy bridge (hexa-core) die shot.png|650px]]
 +
 +
:[[File:ivy bridge (hexa-core) die shot (annotated).png|650px]]
  
 
== See also ==
 
== See also ==
 
* {{intel|Core i7EE|Core i7 Extreme Edition}}
 
* {{intel|Core i7EE|Core i7 Extreme Edition}}

Revision as of 17:56, 9 September 2016

Template:mpu The Core i7-4960X Extreme Edition is a 64-bit hexa-core top-of-the-line MPU introduced by Intel for the enthusiasts market. The i7-4960X served as Intel's flagship microprocessor for the Ivy Bridge microarchitecture - it was superseded by the Haswell-based i7-5960X MPU. Operating at 3.6 GHz with turbo frequency of 4 GHz for a single core, this chip supports 64 GB of memory (DDR3) and has a TDP of 130 Watts.

Cache

Main article: Ivy Bridge's Cache
Cache Info [Edit Values]
L1I$ 192 KB
"KB" is not declared as a valid unit of measurement for this property.
6x32 KB 8-way set associative (per core)
L1D$ 192 KB
"KB" is not declared as a valid unit of measurement for this property.
6x32 KB 8-way set associative (per core)
L2$ 1,536 KB
"KB" is not declared as a valid unit of measurement for this property.
6x256 KB 8-way set associative (per core)
L3$ 15 MB
"MB" is not declared as a valid unit of measurement for this property.
20-way set associative (shared)

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR3-1066, DDR3-1333, DDR3-1600, DDR3-1866
Controllers 1
Channels 4
ECC Support No
Max bandwidth 59.7 GB/s
Max memory 64 GB

Expansions

Template:mpu expansions

Features

Template:mpu features

Die Shot

  • 22 nm process
  • 1,860,000,000 transistors
  • 256.5 mm²
  • 15.0 mm x 17.1 mm
ivy bridge (hexa-core) die shot.png
ivy bridge (hexa-core) die shot (annotated).png

See also

l1d$ description8-way set associative +
l1i$ description8-way set associative +
l2$ description8-way set associative +
l3$ description20-way set associative +