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* '''Bus:''' {{intel|DMI}} (2.5 GT/s) interface
 
* '''Bus:''' {{intel|DMI}} (2.5 GT/s) interface
 
* '''TDP:'''  18, 35 W
 
* '''TDP:'''  18, 35 W
* '''ISA:''' Everything up to {{x86|AES}} ({{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, and {{x86|AES}}), and {{intel|TXT}}.
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* '''ISA:''' Everything up to {{x86|AES}} ({{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, and {{x86|AES}}), {{intel|No-eXecute}}, and {{intel|TXT}}.
 
* '''Tech:''' {{intel|EIST}}, {{intel|VT-x}}, {{intel|VT-d}}, {{intel|Hyper-threading}}, and {{intel|TBT}}.
 
* '''Tech:''' {{intel|EIST}}, {{intel|VT-x}}, {{intel|VT-d}}, {{intel|Hyper-threading}}, and {{intel|TBT}}.
  

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Facts about "Core i5 - Intel"
designerIntel +
first announcedJune 17, 2009 +
first launchedSeptember 2009 +
full page nameintel/core i5 +
instance ofmicroprocessor family +
instruction set architectureIA-32 + and x86-64 +
main designerIntel +
manufacturerIntel +
microarchitectureNehalem +, Westmere +, Sandy Bridge +, Ivy Bridge +, Haswell +, Broadwell +, Skylake +, Kaby Lake +, Coffee Lake + and Ice Lake +
nameIntel Core i5 +
packageFCBGA-1440 +, FCBGA-1364 +, FCBGA-1288 +, FCBGA-1168 +, FCLGA-1155 +, FCLGA-1151 +, FCLGA-1150 +, FCBGA-1023 +, FCPGA-988 + and FCPGA-946 +
process45 nm (0.045 μm, 4.5e-5 mm) +, 32 nm (0.032 μm, 3.2e-5 mm) +, 22 nm (0.022 μm, 2.2e-5 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) +
socketLGA-1151 +, LGA-1150 +, LGA-1155 +, LGA-1156 +, Socket G1 +, Socket G2 + and Socket G3 +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +