From WikiChip
Difference between revisions of "intel/celeron/b810"
< intel‎ | celeron

(Memory controller)
(Expansions)
Line 63: Line 63:
  
 
== Expansions ==
 
== Expansions ==
 +
{{expansions main
 +
|
 +
{{expansions entry
 +
|type=PCIe
 +
|pcie revision=2.0
 +
|pcie lanes=16
 +
|pcie config=1x16
 +
|pcie config 2=2x8
 +
|pcie config 3=1x8+2x4
 +
}}
 +
}}
  
 
== Graphics ==
 
== Graphics ==

Revision as of 20:50, 19 August 2017

Template:mpu

Cache

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1333, DDR3-1066
Supports ECCNo
Max Mem16 GiB
Controllers1
Channels2
Max Bandwidth19.87 GiB/s
20,346.88 MiB/s
21.335 GB/s
21,335.25 MB/s
0.0194 TiB/s
0.0213 TB/s
Bandwidth
Single 9.93 GiB/s
Double 19.87 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 2.0
Max Lanes: 16
Configuration: 1x16, 2x8, 1x8+2x4


Graphics

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
Facts about "Celeron B810 - Intel"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Celeron B810 - Intel#pcie +
has ecc memory supportfalse +
max memory bandwidth19.87 GiB/s (20,346.88 MiB/s, 21.335 GB/s, 21,335.25 MB/s, 0.0194 TiB/s, 0.0213 TB/s) +
max memory channels2 +
supported memory typeDDR3-1333 + and DDR3-1066 +