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== Cache ==
 
== Cache ==
{{main|intel/microarchitectures/airmont#Memory_Hierarchy|l1=Airmont § Cache}}
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{{main|intel/microarchitectures/airmont#Memory_Hierarchy|l1=Airmont's Cache}}
 
{{cache info
 
{{cache info
|l1i cache=128 KiB
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|l1i cache=128 KB
|l1i break=4x32 KiB
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|l1i break=4x32 KB
 
|l1i desc=8-way set associative
 
|l1i desc=8-way set associative
 
|l1i extra=(per core)
 
|l1i extra=(per core)
|l1d cache=96 KiB
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|l1d cache=96 KB
|l1d break=4x24 KiB
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|l1d break=4x24 KB
 
|l1d desc=6-way set associative
 
|l1d desc=6-way set associative
 
|l1d extra=(per core)
 
|l1d extra=(per core)
|l2 cache=2 MiB
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|l2 cache=2 MB
|l2 break=2x1 MiB
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|l2 break=2x1 MB
 
|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
 
|l2 extra=(per 2 cores)
 
|l2 extra=(per 2 cores)

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Facts about "Atom x5-Z8500 - Intel"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Atom x5-Z8500 - Intel#io +
base frequency1,440 MHz (1.44 GHz, 1,440,000 kHz) +
core count4 +
core nameCherry Trail +
core steppingC0 +
designerIntel +
familyAtom x5 +
first announcedMarch 2, 2015 +
first launchedMarch 2, 2015 +
full page nameintel/atom x5/x5-z8500 +
has featureintegrated gpu +, SD Card support +, SDIO support +, eMMC support +, Low Power Engine +, Advanced Encryption Standard Instruction Set Extension +, Burst Performance Technology + and Enhanced SpeedStep Technology +
has intel burst performance technologytrue +
has intel enhanced speedstep technologytrue +
has locked clock multipliertrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
integrated gpuHD Graphics (Cherry Trail) +
integrated gpu base frequency200 MHz (0.2 GHz, 200,000 KHz) +
integrated gpu max frequency600 MHz (0.6 GHz, 600,000 KHz) +
integrated gpu max memory8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB) +
l1d$ description6-way set associative +
l1d$ size96 KiB (98,304 B, 0.0938 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description16-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
l3$ descriptionNo L3$ +
l3$ size0 MiB (0 KiB, 0 B, 0 GiB) +
ldateMarch 2, 2015 +
manufacturerIntel +
market segmentMobile +
max cpu count1 +
max memory8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) +
max operating temperature90 °C +
max pcie lanes2 +
microarchitectureAirmont +
min operating temperature0 °C +
model numberx5-Z8500 +
nameIntel Atom x5-Z8500 +
part numberFJ8066401715814 + and FJ8066401715842 +
platformCherry Trail +
process14 nm (0.014 μm, 1.4e-5 mm) +
s-specSR27N + and SR2GN +
sdp2 W (2,000 mW, 0.00268 hp, 0.002 kW) +
seriesZ8000 +
smp max ways1 +
technologyCMOS +
thread count4 +
turbo frequency (1 core)2,240 MHz (2.24 GHz, 2,240,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +