From WikiChip
Difference between revisions of "intel/atom/z620"
< intel‎ | atom

Line 91: Line 91:
 
'''Atom Z620''' is an ultra-low power {{arch|32}} [[x86]] system on a chip designed by [[Intel]] and introduced in early [[2010]]. The Z620, which is based on the {{intel|Bonnell|l=arch}} microarchitecture ({{intel|Lincroft|l=core}} core), is fabricated on a [[45 nm process]]. This SoC incorporates a single core operating at 900 MHz with a low frequency mode of 600 MHz and a burst frequency of 1.5 GHz. The chip has a TDP of 1.3 W and supporting up to a 2 GiB of single-channel DDR2-800 memory. Additionally, the Z620 incorporates a {{imgtec|PowerVR SGX 535|GMA 600}} [[IGP]] operating at 400 MHz.
 
'''Atom Z620''' is an ultra-low power {{arch|32}} [[x86]] system on a chip designed by [[Intel]] and introduced in early [[2010]]. The Z620, which is based on the {{intel|Bonnell|l=arch}} microarchitecture ({{intel|Lincroft|l=core}} core), is fabricated on a [[45 nm process]]. This SoC incorporates a single core operating at 900 MHz with a low frequency mode of 600 MHz and a burst frequency of 1.5 GHz. The chip has a TDP of 1.3 W and supporting up to a 2 GiB of single-channel DDR2-800 memory. Additionally, the Z620 incorporates a {{imgtec|PowerVR SGX 535|GMA 600}} [[IGP]] operating at 400 MHz.
  
 +
This chip communicates with the [[southbridge]] chipset (PCH MP30) over two buses: cDMI and cDVO. Both buses go from the SoC to the chipset. cDMI, which is used as the data interface link, operates at 100 MHz using a quad-pumped rate (i.e. 400 MT/s). That bus is composed of an 8-bit transmit and 8-bit receive. The cDVO, which is used as a unidirectional display data link is a quad-pumped 6-bit bus operating 100 MHz for a 400 MT/s effective rate. This model uses CMOS signaling for both buses.
 
== Cache ==
 
== Cache ==
 
{{main|intel/microarchitectures/bonnell#Memory_Hierarchy|l1=Bonnell § Cache}}
 
{{main|intel/microarchitectures/bonnell#Memory_Hierarchy|l1=Bonnell § Cache}}

Revision as of 23:49, 22 April 2017

Template:mpu Atom Z620 is an ultra-low power 32-bit x86 system on a chip designed by Intel and introduced in early 2010. The Z620, which is based on the Bonnell microarchitecture (Lincroft core), is fabricated on a 45 nm process. This SoC incorporates a single core operating at 900 MHz with a low frequency mode of 600 MHz and a burst frequency of 1.5 GHz. The chip has a TDP of 1.3 W and supporting up to a 2 GiB of single-channel DDR2-800 memory. Additionally, the Z620 incorporates a GMA 600 IGP operating at 400 MHz.

This chip communicates with the southbridge chipset (PCH MP30) over two buses: cDMI and cDVO. Both buses go from the SoC to the chipset. cDMI, which is used as the data interface link, operates at 100 MHz using a quad-pumped rate (i.e. 400 MT/s). That bus is composed of an 8-bit transmit and 8-bit receive. The cDVO, which is used as a unidirectional display data link is a quad-pumped 6-bit bus operating 100 MHz for a 400 MT/s effective rate. This model uses CMOS signaling for both buses.

Cache

Main article: Bonnell § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$56 KiB
57,344 B
0.0547 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1x32 KiB8-way set associative 
L1D$24 KiB
24,576 B
0.0234 MiB
1x24 KiB6-way set associativewrite-back

L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  1x512 KiB8-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR-400, DDR2-800
Supports ECCNo
Max Mem2 GiB
Controllers1
Channels1
Width32 bit
Max Bandwidth2.98 GiB/s
3,051.52 MiB/s
3.2 GB/s
3,199.751 MB/s
0.00291 TiB/s
0.0032 TB/s
Bandwidth
Single 2.98 GiB/s
Physical Address (PAE)32 bit

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
USB
Revision2.0
Ports4
UART

GP I/OYes


Graphics

This chip incroporates the "GMA 600" integrated graphics which is actually a re-branded licensed Imagination PowerVR SGX 535 IGP.

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR SGX535
DesignerImagination Technologies
Max Displays1
Max Memory256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
Frequency200 MHz
0.2 GHz
200,000 KHz
OutputDSI, LVDS

Max Resolution
DSI1024x600
LVDS1366x768

Standards
Direct3D9.0c
OpenGL2.1
OpenGL ES1.1, 2.0
OpenVG1.1

Additional Features
Intel Clear Video
  • Supports hardware-accelerated HD video decode (MPEG4 part 2, H.264, WMV, and VC1)
  • Supports hardware-accelerated HD video encode (MPEG4 part 2 and H.264)

Features

Facts about "Atom Z620 - Intel"
has ecc memory supportfalse +
has featureHyper-Threading Technology +, Burst Performance Technology + and Enhanced SpeedStep Technology +
has intel burst performance technologytrue +
has intel enhanced speedstep technologytrue +
has simultaneous multithreadingtrue +
integrated gpuPowerVR SGX535 +
integrated gpu base frequency200 MHz (0.2 GHz, 200,000 KHz) +
integrated gpu designerImagination Technologies +
integrated gpu max memory256 MiB (262,144 KiB, 268,435,456 B, 0.25 GiB) +
l1$ size56 KiB (57,344 B, 0.0547 MiB) +
l1d$ description6-way set associative +
l1d$ size24 KiB (24,576 B, 0.0234 MiB) +
l1i$ description8-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
l2$ description8-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
max memory bandwidth2.98 GiB/s (3,051.52 MiB/s, 3.2 GB/s, 3,199.751 MB/s, 0.00291 TiB/s, 0.0032 TB/s) +
max memory channels1 +
supported memory typeDDR-400 + and DDR2-800 +