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Difference between revisions of "intel/atom/z510p"
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| − | '''Z510P''' is an ultra-low power {{arch|32}} [[x86]] microprocessor introduced by [[Intel]] in early 2009 specifically for Mobile Internet Devices (MID). The Z510P, which is based on the {{intel|Bonnell|l=arch}} microarchitecture ({{intel|Silverthorne|l=core}} core), is manufactured on a [[45 nm process]]. This processor operates at 1.1 Ghz with a TDP of | + | '''Z510P''' is an ultra-low power {{arch|32}} [[x86]] microprocessor introduced by [[Intel]] in early 2009 specifically for Mobile Internet Devices (MID). The Z510P, which is based on the {{intel|Bonnell|l=arch}} microarchitecture ({{intel|Silverthorne|l=core}} core), is manufactured on a [[45 nm process]]. This processor operates at 1.1 Ghz with a TDP of 2 W. The MPU features a legacy 400 MT/s [[front-side bus]] capable of communicating with the {{intel|Poulsbo|l=chipset}} chipset in both low-power [[CMOS]] mode as well as normal [[GTL]] mode (which also works with other chipsets). |
| − | This model is identical to the {{\\|Z510}} but comes in a large package. | + | This model is identical to the {{\\|Z510}} but comes in a large package. This processor has a TDP of 2 W when {{intel|Hyper-Threading}} is disabled and 2.2 W when enabled. |
Revision as of 20:00, 1 April 2017
Template:mpu Z510P is an ultra-low power 32-bit x86 microprocessor introduced by Intel in early 2009 specifically for Mobile Internet Devices (MID). The Z510P, which is based on the Bonnell microarchitecture (Silverthorne core), is manufactured on a 45 nm process. This processor operates at 1.1 Ghz with a TDP of 2 W. The MPU features a legacy 400 MT/s front-side bus capable of communicating with the Poulsbo chipset in both low-power CMOS mode as well as normal GTL mode (which also works with other chipsets).
This model is identical to the Z510 but comes in a large package. This processor has a TDP of 2 W when Hyper-Threading is disabled and 2.2 W when enabled.
