Semiconductor & Computer Engineering
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Difference between revisions of "intel/80486/486sx2-50"
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{{mpu | {{mpu | ||
| name = Intel i486SX2-50 | | name = Intel i486SX2-50 | ||
| − | + | | image = Ic-photo-intel-A80486SX2-50-(486SX2).png | |
| − | | image = | ||
| image size = | | image size = | ||
| − | | caption = | + | | caption = A80486SX2-50, S-Spec SX845 |
| designer = Intel | | designer = Intel | ||
| manufacturer = Intel | | manufacturer = Intel | ||
Revision as of 17:12, 11 May 2016
Template:mpu i486SX2-50 was a fourth-generation x86 microprocessor introduced by Intel in the early 1990s. This chip, which is based on the 80486 microarchitecture, had a clock doubler operating at 50 MHz, twice the bus speed. In contrast to the i486DX chips, the i486SX line had no functional FPU on-die.
Contents
Cache
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KB "KB" is not declared as a valid unit of measurement for this property. |
1x8 KB 4-way set associative (unified, write-through policy) |
Graphics
This chip had no integrated graphics processing unit.
Features
- System Management Mode (SMM)
