Semiconductor & Computer Engineering
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Difference between revisions of "intel/80486/486dx2-50"
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{{mpu | {{mpu | ||
| name = Intel i486DX2-50 | | name = Intel i486DX2-50 | ||
| − | + | | image = Ic-photo-Intel--SB80486DX2-50--(486-CPU).JPG | |
| − | | image = | ||
| image size = | | image size = | ||
| − | | caption = | + | | caption = SB80486DX2-50 |
| designer = Intel | | designer = Intel | ||
| manufacturer = Intel | | manufacturer = Intel | ||
Revision as of 17:05, 11 May 2016
Template:mpu i486DX2-50 was a fourth-generation x86 microprocessor introduced by Intel in 1992. This chip, which is based on the 80486 microarchitecture, had a clock doubler operating at 50 MHz, twice the bus frequency. Like the original i486DX, this chip implemented the 80387 FPU on-die and incorporated System Management Mode (SMM).
Contents
Cache
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KB "KB" is not declared as a valid unit of measurement for this property. |
1x8 KB 4-way set associative (unified, write-through policy ) |
Graphics
This chip had no integrated graphics processing unit.
Features
- System Management Mode (SMM)
