Semiconductor & Computer Engineering
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Difference between revisions of "intel/80486/486dx2-50"
| Line 28: | Line 28: | ||
| bus rate = 25 MT/s | | bus rate = 25 MT/s | ||
| clock multiplier = 2 | | clock multiplier = 2 | ||
| − | | s-spec = | + | | s-spec = SX626 |
| + | | s-spec 2 = SX627 | ||
| + | | s-spec 3 = SX641 | ||
| + | | s-spec 4 = SX721 | ||
| + | | s-spec 5 = SX738 | ||
| + | | s-spec 6 = SX749 | ||
| + | | s-spec 7 = SX760 | ||
| + | | s-spec 8 = SX761 | ||
| + | | s-spec 9 = SX768 | ||
| + | | s-spec 10 = SX808 | ||
| + | | s-spec 11 = SX912 | ||
| + | | s-spec 12 = SX954 | ||
| s-spec es = | | s-spec es = | ||
| − | | s-spec qs = | + | | s-spec qs = Q0382 |
| − | | s-spec qs 2 = | + | | s-spec qs 2 = Q0424 |
| − | | cpuid = | + | | cpuid = 432 |
| + | | cpuid 2 = 433 | ||
| + | | cpuid 3 = 435 | ||
| + | | cpuid 4 = 436 | ||
| microarch = 80486 | | microarch = 80486 | ||
| Line 52: | Line 66: | ||
| electrical = Yes | | electrical = Yes | ||
| − | | power = 3. | + | | power = 3.88 W |
| v core = 5 V | | v core = 5 V | ||
| v core tolerance = 5% | | v core tolerance = 5% | ||
Revision as of 16:33, 11 May 2016
Template:mpu i486DX2-50 was a fourth-generation x86 microprocessor introduced by Intel in 1992. This chip, which is based on the 80486 microarchitecture, had a clock doubler operating at 50 MHz, twice the bus frequency. Like the original i486DX, this chip implemented the 80387 FPU on-die and incorporated System Management Mode (SMM).
Contents
Cache
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KB "KB" is not declared as a valid unit of measurement for this property. |
1x8 KB 4-way set associative (unified, write-through policy ) |
Graphics
This chip had no integrated graphics processing unit.
Features
- System Management Mode (SMM)
