From WikiChip
Revision history of "intel/xeon silver/4216"
View logs for this page

Diff selection: Mark the radio boxes of the revisions to compare and hit enter or the button at the bottom.
Legend: (cur) = difference with latest revision, (prev) = difference with preceding revision, m = minor edit.

Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Silver 4216 - Intel#pcie +
base frequency2,100 MHz (2.1 GHz, 2,100,000 kHz) +
chipsetLewisburg +
clock multiplier21 +
core count16 +
core family6 +
core nameCascade Lake SP +
core steppingL1 + and L0 +
designerIntel +
familyXeon Silver +
first announcedApril 2, 2019 +
first launchedApril 2, 2019 +
full page nameintel/xeon silver/4216 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Extended Page Tables +, Transactional Synchronization Extensions +, Intel VT-d + and Deep Learning Boost +
has intel deep learning boosttrue +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l1d$ description8-way set associative +
l1d$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l1i$ description8-way set associative +
l1i$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l2$ description16-way set associative +
l2$ size16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) +
l3$ description11-way set associative +
l3$ size22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) +
ldateApril 2, 2019 +
main imageFile:cascade lake sp (front).png +
manufacturerIntel +
market segmentServer +
max case temperature352.15 K (79 °C, 174.2 °F, 633.87 °R) +
max cpu count2 +
max memory1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth107.3 GiB/s (186.702 GB/s, 109,875.2 MiB/s, 0.105 TiB/s, 0.115 TB/s) +
max memory channels6 +
microarchitectureCascade Lake +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model number4216 +
nameXeon Silver 4216 +
packageFCLGA-3647 +
part numberCD8069504213901 + and BX806954216 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 1,002.00 (€ 901.80, £ 811.62, ¥ 103,536.66) + and $ 1,012.00 (€ 910.80, £ 819.72, ¥ 104,569.96) +
release price (box)$ 1,012.00 (€ 910.80, £ 819.72, ¥ 104,569.96) +
release price (tray)$ 1,002.00 (€ 901.80, £ 811.62, ¥ 103,536.66) +
s-specSRFBB +
s-spec (qs)QRG8 +
series4200 +
smp interconnectUPI +
smp interconnect links2 +
smp interconnect rate9.6 GT/s +
smp max ways2 +
socketSocket P + and LGA-3647 +
supported memory typeDDR4-2400 +
tdp100 W (100,000 mW, 0.134 hp, 0.1 kW) +
technologyCMOS +
thread count32 +
turbo frequency (1 core)3,200 MHz (3.2 GHz, 3,200,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +