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=== GT1 (ULP) === | === GT1 (ULP) === | ||
− | GT1 is the most compact configuration offering two benefits: reduced cost and reduced power. GT1 is made of 1 slice containing 2 subslices with 6 EUs/subslice for a total of 12 EUs. With the scale-down, GT1 changes the ratio to 6:1 EU:sampler ratio. Note that this does retains the same ratio of 12 texels/clock and 8 pixels/clock at the backend. This configuration is better suited for some of the low power | + | GT1 is the most compact configuration offering two benefits: reduced cost and reduced power. GT1 is made of 1 slice containing 2 subslices with 6 EUs/subslice for a total of 12 EUs. With the scale-down, GT1 changes the ratio to 6:1 EU:sampler ratio. Note that this does retains the same ratio of 12 texels/clock and 8 pixels/clock at the backend. This configuration is better suited for some of the low power worlkload (e.g. ASTC-LDR+HDR, ETC1/2 compression). Note that software stack remains unchanged compared to the larger models. |
[[File:gen9 lp gt1 block diagram.svg|600px]] | [[File:gen9 lp gt1 block diagram.svg|600px]] |
Facts about "Gen9 - Microarchitectures - Intel"
codename | Gen9 + |
designer | Intel + |
first launched | August 5, 2015 + |
full page name | intel/microarchitectures/gen9 + |
instance of | microarchitecture + |
manufacturer | Intel + |
microarchitecture type | GPU + |
name | Gen9 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |