From WikiChip
Difference between revisions of "ibm/microarchitectures/z15"
< ibm

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|isa=z/Architecture
 
|isa=z/Architecture
 
|l1i=128 KiB
 
|l1i=128 KiB
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|l1i per=core
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|l1i desc=8-way set associative
 
|l1d=128 KiB
 
|l1d=128 KiB
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|l1d per=core
 +
|l1d desc=8-way set associative
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|l3=256 MiB
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|l3 per=chip
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|l3 desc=32-way set associative
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|l4=960 MiB
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|l4 per=drawer
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|l4 desc=60-way set associative
 
|predecessor=z14
 
|predecessor=z14
 
|predecessor link=ibm/microarchitectures/z14
 
|predecessor link=ibm/microarchitectures/z14

Revision as of 19:42, 14 September 2019

Edit Values
z15 µarch
General Info
Arch TypeCPU
DesignerIBM
ManufacturerGlobalFoundries
IntroductionSeptember 12, 2019
Process14 nm
Core Configs12
Pipeline
TypeSuperscalar, Pipelined
OoOEYes
SpeculativeYes
Reg RenamingYes
Instructions
ISAz/Architecture
Cache
L1I Cache128 KiB/core
8-way set associative
L1D Cache128 KiB/core
8-way set associative
L3 Cache256 MiB/chip
32-way set associative
L4 Cache960 MiB/drawer
60-way set associative
Succession

z15 is the successor to the z14, a 14 nm z/Architecture mainframe microarchitecture designed by IBM and introduced in 2019.


Under construction icon-blue.svg This article is a work in progress!


Process Technology

IBM fabricates its z15 microprocessors and system controllers on GlobalFoundries's 14 nm (14HP) FinFET Silicon-On-Insulator (SOI) process featuring highly-dense deep trench structures used for high-density eDRAM.

Release Dates

The z15 was launched by IBM on September 12, 2019. General availability of the z15 mainframe started September 23.

Architecture

Key changes from z14

  • Higher scalability
    • Up to 190-way multiprocessing (from 170-way)
  • Central Processor (CP)
    • 2 more cores (12, up from 10)
    • Core
      • 10-13% higher IPC (IBM claim)
      • Front-end
        • Improved branch predictor
          • New TAGE predictor
          • BTB pre-buffer (BTBp) replaced by a simpler write buffer
            • single double-bandwidth port (two independentread ports)
          • 2x larger L1 BTB (8 sets of 2K rows, up from 4 sets of 2K rows)
      • Back-end
        • Larger GCT (60 groups, up from 48 groups)
          • Wider retire (12 instructions/cycle, up from 10)
        • Larger Issue Queues (2 x 36-entry, up from 2 x 30-entry)
        • 2x larger mapper (128-entry, up from 64-entry)
        • Larger integer physical register files (???, up from 120 entries)
        • Larger vector physical register files (???, up from 127 entries)
      • Execution engine
        • New Modulo Arithmetic (MA) unit
      • Memory subsystem
    • Shared L3
      • 2x larger L3 (256 MiB, up from 128 MiB)
    • New integration
      • Nest Acceleration Unit (NXU)
  • System Controller (SC)
    • 1.4x Larger L4 cache (960 MiB, up from 672 MiB)

Overview

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Mainframe

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System

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Drawer

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Central Processor

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Core

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Die

Central Processor (CP) Chip

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Core

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System Controller (SC) Chip

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codenamez15 +
core count12 +
designerIBM +
first launchedSeptember 12, 2019 +
full page nameibm/microarchitectures/z15 +
instance ofmicroarchitecture +
instruction set architecturez/Architecture +
manufacturerGlobalFoundries +
microarchitecture typeCPU +
namez15 +
process14 nm (0.014 μm, 1.4e-5 mm) +