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POWER9 - Microarchitectures - IBM
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POWER9 µarch
General Info
Arch TypeCPU
DesignerIBM
ManufacturerGlobalFoundries
IntroductionAugust, 2017
Phase-outAugust, 2018
Process14 nm
Pipeline
TypeSuperscalar
SpeculativeYes
Reg RenamingYes
Stages12-16
Instructions
ISAPower ISA v3.0
Cache
L1I Cache32 KiB/core
L1D Cache32 KiB/core
L2 Cache512 KiB/core
L3 Cache120 MiB/chip
Succession

POWER9 is the 14 nm microarchitecture for IBM's family of POWER9 processors set to be introduced in the 2nd half of 2017. POWER9 is a successor to the POWER8 microarchitecture.

Process Technology

POWER9 is set to be fabricated on GlobalFoundries' 14 nm FinFET process, the same process that's used by AMD for their Zen microarchitecture.

Compatibility

Initial support for POWER9 started with Linux Kernel 4.8.

Vendor OS Version Notes
IBM AIX 7.? Support
IBM i  ? Support
Linux Linux Kernel 4.8 Initial Support
Wind River VxWorks VxWorks 7.? Support

Compiler support

Compiler CPU Arch-Favorable
GCC -mcpu=pwr9 -mtune=pwr9
LLVM -mcpu=pwr9 -mtune=pwr9
XL C/C++ -mcpu=pwr9 -mtune=pwr9

Architecture

Key changes from POWER8

  • 14 nm process (from 22 nm)
    • 17-layer metal stack
    • 8,000,000,000 transistors
  • Support for Power ISA v3.0
  • Higher single-thread performance
  • New highly modular architecture
  • Shorter pipeline
    • 5 stages eliminated from fetch to compute vs POWER8
  • Cache
    • 120 MiB NUCA L3
      • eDRAM
      • 7 TB/s on-chip bandwidth
  • Hardware Acceleration
  • I/O Subsystem
    • PCIe Gen4
    • Local SMP - 16 GT/s per lane interface
    • Remote SMP - 25 GT/s per lane interface
      • 48-96 lanes capability
      • IBM's SMP connect for their scale-up systems
      • Also available for the accelerators
  • Virtualization
    • QoS assistance
    • New Interrupt architecture
    • Workload-optimized frequency
    • Hardware enforced trusted execution

Pipeline

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Die Shot

Tetracosa-Core

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See also

codenamePOWER9 +
designerIBM +
first launchedAugust 2017 +
full page nameibm/microarchitectures/power9 +
instance ofmicroarchitecture +
instruction set architecturePower ISA v3.0 +
manufacturerGlobalFoundries +
microarchitecture typeCPU +
namePOWER9 +
phase-outAugust 2018 +
pipeline stages (max)16 +
pipeline stages (min)12 +
process14 nm (0.014 μm, 1.4e-5 mm) +