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** L1I Cache | ** L1I Cache | ||
*** 32 [[KiB]], 8-way set associative | *** 32 [[KiB]], 8-way set associative | ||
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*** Per SMT4 Core | *** Per SMT4 Core | ||
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** L1D Cache | ** L1D Cache | ||
*** 32 KiB, 8-way set associative | *** 32 KiB, 8-way set associative | ||
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*** Per SMT4 Core | *** Per SMT4 Core | ||
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** L2 Cache | ** L2 Cache | ||
− | *** | + | *** 256 KiB per SMT4 core |
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− | |||
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** L3 Cache | ** L3 Cache | ||
*** 120 MiB [[eDRAM]] | *** 120 MiB [[eDRAM]] | ||
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*** 12 chunks (regions) of 10 MiB 20-way set associative | *** 12 chunks (regions) of 10 MiB 20-way set associative | ||
*** 7 TB/s on-chip bandwidth | *** 7 TB/s on-chip bandwidth |
Facts about "POWER9 - Microarchitectures - IBM"
codename | POWER9 + |
core count | 24 +, 4 +, 8 +, 12 +, 16 + and 20 + |
designer | IBM + |
first launched | August 2017 + |
full page name | ibm/microarchitectures/power9 + |
instance of | microarchitecture + |
instruction set architecture | Power ISA v3.0B + |
manufacturer | GlobalFoundries + |
microarchitecture type | CPU + |
name | POWER9 + |
phase-out | 2020 + |
pipeline stages (max) | 16 + |
pipeline stages (min) | 12 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |