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=== Acceleration Platform (POWERAccel) === | === Acceleration Platform (POWERAccel) === | ||
[[File:p9links.png|250px|right]] | [[File:p9links.png|250px|right]] | ||
− | '''POWERAccel''' is the collective name for all the interfaces and acceleration protocols provided by the POWER microarchitecture. POWER9 offers two sets of acceleration attachments: [[PCIe]] Gen4 which offers 48 lanes at 192 GiB/s duplex bandwidth and a new 25G link which offers an additional 48 lanes delivering up to 300 GiB/s of duplex bandwidth. On top of the two physical interfaces are a set of open standard protocols that integrated onto those signaling interfaces. The four prominent standards are: | + | '''POWERAccel''' is the term collective name for all the interfaces and acceleration protocols provided by the POWER microarchitecture. POWER9 offers two sets of acceleration attachments: [[PCIe]] Gen4 which offers 48 lanes at 192 GiB/s duplex bandwidth and a new 25G link which offers an additional 48 lanes delivering up to 300 GiB/s of duplex bandwidth. On top of the two physical interfaces are a set of open standard protocols that integrated onto those signaling interfaces. The four prominent standards are: |
* [[CAPI]] 2.0 - POWER9 introduces CAPI 2.0 over [[PCIe]] which quadruples the bandwidth offered by the original CAPI protocol offered in {{\\|POWER8}}. | * [[CAPI]] 2.0 - POWER9 introduces CAPI 2.0 over [[PCIe]] which quadruples the bandwidth offered by the original CAPI protocol offered in {{\\|POWER8}}. |
Facts about "POWER9 - Microarchitectures - IBM"
codename | POWER9 + |
core count | 24 +, 4 +, 8 +, 12 +, 16 + and 20 + |
designer | IBM + |
first launched | August 2017 + |
full page name | ibm/microarchitectures/power9 + |
instance of | microarchitecture + |
instruction set architecture | Power ISA v3.0B + |
manufacturer | GlobalFoundries + |
microarchitecture type | CPU + |
name | POWER9 + |
phase-out | 2020 + |
pipeline stages (max) | 16 + |
pipeline stages (min) | 12 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |