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Difference between revisions of "ibm/microarchitectures/power8"
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* [[Dodeca-Core]] | * [[Dodeca-Core]] | ||
* IBM's [[22 nm process|22 nm SOI process]] | * IBM's [[22 nm process|22 nm SOI process]] | ||
| + | * 15 metal layers | ||
* 4,200,000,000 transistors | * 4,200,000,000 transistors | ||
* 649 mm² die size | * 649 mm² die size | ||
Revision as of 14:59, 18 May 2017
| Edit Values | |
| POWER8 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | IBM |
| Manufacturer | IBM |
| Introduction | August, 2013 |
| Phase-out | June, 2014 |
| Process | 22 nm |
| Core Configs | 4, 6, 8, 10, 12 |
| Pipeline | |
| Type | Superscalar |
| Speculative | Yes |
| Reg Renaming | Yes |
| Stages | 15-23 |
| Cache | |
| L1I Cache | 32 KiB/core 8-way set associative |
| L1D Cache | 64 KiB/core 8-way set associative |
| L2 Cache | 512 KiB/core |
| L3 Cache | 8 MiB/core |
| L4 Cache | 128 MiB/chip |
| Succession | |
POWER8 is the Power microarchitecture for IBM's family of POWER8 processors that was introduced in 2014. POWER8 is the successor to POWER7+.
Architectures
Key changes from POWER7/+
 |
This section is empty; you can help add the missing info by editing this page. |
Die
Dodeca-Core
- Dodeca-Core
- IBM's 22 nm SOI process
- 15 metal layers
- 4,200,000,000 transistors
- 649 mm² die size
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Facts about "POWER8 - Microarchitectures - IBM"
| codename | POWER8 + |
| core count | 4 +, 6 +, 8 +, 10 + and 12 + |
| designer | IBM + |
| first launched | August 2013 + |
| full page name | ibm/microarchitectures/power8 + |
| instance of | microarchitecture + |
| manufacturer | IBM + |
| microarchitecture type | CPU + |
| name | POWER8 + |
| phase-out | June 2014 + |
| pipeline stages (max) | 23 + |
| pipeline stages (min) | 15 + |
| process | 22 nm (0.022 μm, 2.2e-5 mm) + |
