Semiconductor & Computer Engineering
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{{ibm title|Centaur}} | {{ibm title|Centaur}} | ||
'''Centaur''' is is a memory buffer chip designed by [[IBM]] for their {{ibm|POWER}} scale-up microprocessors. First introduced with the {{ibm|POWER8|l=arch}} microarchitecture, each Centaur chip includes 16 MiB of [[eDRAM]] and four DDR3/DDR4 [[DRAM]] ports. | '''Centaur''' is is a memory buffer chip designed by [[IBM]] for their {{ibm|POWER}} scale-up microprocessors. First introduced with the {{ibm|POWER8|l=arch}} microarchitecture, each Centaur chip includes 16 MiB of [[eDRAM]] and four DDR3/DDR4 [[DRAM]] ports. | ||
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| + | == Overview == | ||
| + | Due to the inherent limitations of scaling [[DDR]] to a large number of channels, IBM uses an array of [[SerDes]] on the POWER die in order to communicate with an intermediate memory buffer chip, called '''Centaur''', which is used to access a larger set of DDR devices. Centaur is fabricated on [[22 nm]] [[SOI]], has 16 MiB of [[eDRAM]], and includes four [[DDR3]]/[[DDR4]] ports support 1 DIMM per port. | ||
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| + | {{ibm|POWER8|l=arch}} and {{ibm|POWER9|l=arch}} processors that rely on Centaur communicate in a memory-channel-agnostic way. Operations such as cache-line reads/writes are sent to the chip as high-level commands. Scheduling is no longer tightly controlled by the microprocessor as it did in prior designs (e.g., {{ibm|POWER7|l=arch}}. It's worth noting that the agnostic attribute of Centaur, new memory technologies (e.g., [[storage-class memory]]) can be introduced without any fundamental changes to the microprocessor itself. | ||
[[category:ibm]] | [[category:ibm]] | ||
[[Category:memory subsystem]] | [[Category:memory subsystem]] | ||
Revision as of 22:56, 27 September 2018
Centaur is is a memory buffer chip designed by IBM for their POWER scale-up microprocessors. First introduced with the POWER8 microarchitecture, each Centaur chip includes 16 MiB of eDRAM and four DDR3/DDR4 DRAM ports.
Overview
Due to the inherent limitations of scaling DDR to a large number of channels, IBM uses an array of SerDes on the POWER die in order to communicate with an intermediate memory buffer chip, called Centaur, which is used to access a larger set of DDR devices. Centaur is fabricated on 22 nm SOI, has 16 MiB of eDRAM, and includes four DDR3/DDR4 ports support 1 DIMM per port.
POWER8 and POWER9 processors that rely on Centaur communicate in a memory-channel-agnostic way. Operations such as cache-line reads/writes are sent to the chip as high-level commands. Scheduling is no longer tightly controlled by the microprocessor as it did in prior designs (e.g., POWER7. It's worth noting that the agnostic attribute of Centaur, new memory technologies (e.g., storage-class memory) can be introduced without any fundamental changes to the microprocessor itself.
