Semiconductor & Computer Engineering
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== Architecture == | == Architecture == | ||
| − | === Key changes from {{\\|TaiShan | + | === Key changes from {{\\|TaiShan v100}} === |
* [[TSMC]] [[7 nm|7 nm HPC process]] (from [[16 nm]]) | * [[TSMC]] [[7 nm|7 nm HPC process]] (from [[16 nm]]) | ||
* 2x [[core count]] (64, up from 32) | * 2x [[core count]] (64, up from 32) | ||
Revision as of 10:41, 3 May 2019
| Edit Values | |
| TaiShan v110 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | HiSilicon |
| Manufacturer | TSMC |
| Introduction | 2019 |
| Process | 7 nm |
| Core Configs | 32, 48, 64 |
| Pipeline | |
| Type | Superscalar, Superpipeline |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Decode | 4-way |
| Instructions | |
| ISA | ARMv8.2-A |
| Extensions | NEON |
| Cache | |
| L1I Cache | 64 KiB/core |
| L1D Cache | 64 KiB/core |
| L2 Cache | 512 KiB/core |
| L3 Cache | 1 MiB/core |
| Succession | |
TaiShan v110 is the successor to the TaiShan v100, a high-performance ARM server microarchitecture designed by HiSilicon for Huawei's own TaiShan servers.
Contents
Brands
TaiShan-based CPUs are branded as the Kunpeng 920 series.
Release Dates
Kunpeng 920 CPUs were officially launched in early 2019.
Architecture
Key changes from TaiShan v100
- TSMC 7 nm HPC process (from 16 nm)
- 2x core count (64, up from 32)
This list is incomplete; you can help by expanding it.
Block Diagram
Entire Chip
Memory Hierarchy
- Cache
- L1I Cache
- 64 KiB/core, private
- L1D Cache
- 64 KiB/core, private
- L2 Cache
- 512 KiB/core, private
- L3 Cache
- 1 MiB/core
- Shared by all cores
- System DRAM
- 1 TiB Max Memory / socket
- 8 Channels
- DDR4, up to 2933 MT/s
- 1 DPC and 2 DPC support
- 8 B/cycle/channel (@ memory clock)
- ECC, SDDC, DDDC
- L1I Cache
Overview
 |
This section is empty; you can help add the missing info by editing this page. |
Core
| |
This section is empty; you can help add the missing info by editing this page. |
MCP physical design
The SoC itself comprises 3 dies - two Super CPU Cluster (SCCL) compute dies and a Super IO Cluster (SICL). The SCCL compute dies contains 8 CPU Clusters (CCLs), memory controllers, and the L3 cache block. There are eight CCLs on each of the SICL dies for a total of 64 cores. The CCLs are TaiShan V110 quadplex along with the L3 cache tags partition. The Super IO Clusters include the various I/O peripherals including PCIe Gen 4, SAS, the network interface controllers, and the Hydra links.
Scalability
Each chip incorporates three Hydra interface ports. The Hydra interface facilitates the cache coherency between the dies on the chip. Every link supports 240 Gb/s (30 GB/s) of peak bandwidth for a total aggregated bandwidth of 720 Gb/s (90 GB/s) in a 2-way symmetric multiprocessing configuration.
With all three links, there is also support for 4-way SMP. In this configuration, one link from each socket is connected to another socket for an all-for-all connection.
Die
- TSMC 7 nm HPC
- 20,000,000,000 transistors
- 3-4 dies
All TaiShan Chips
| |
This section is empty; you can help add the missing info by editing this page. |
Bibliography
- Huawei. Personal Communication. 2019
- Huawei Connect 2018. October 2018
- HiSilicon Event. January 7, 2019
| codename | TaiShan v110 + |
| core count | 32 +, 48 + and 64 + |
| designer | HiSilicon + |
| first launched | 2019 + |
| full page name | hisilicon/microarchitectures/taishan v110 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8.2-A + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | TaiShan v110 + |
| process | 7 nm (0.007 μm, 7.0e-6 mm) + |
