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Difference between revisions of "hisilicon/microarchitectures/taishan v110"
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== Scalability ==
 
== Scalability ==
There are three cache coherent ports on each SoC. Every port supports 240 Gb/s (30 GB/s) of peak bandwidth for a total aggregated bandwidth of 720 Gb/s (90 GB/s) in a 2-way [[symmetric multiprocessing]] configuration.
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Each chip incorporates three Hydra interface ports. The Hydra interface facilitates the cache coherency between the dies on the chip. Every link supports 240 Gb/s (30 GB/s) of peak bandwidth for a total aggregated bandwidth of 720 Gb/s (90 GB/s) in a 2-way [[symmetric multiprocessing]] configuration.
  
 
:[[File:Kunpeng 920 2smp.svg|600px]]
 
:[[File:Kunpeng 920 2smp.svg|600px]]

Revision as of 08:31, 3 May 2019

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TaiShan v110 µarch
General Info
Arch TypeCPU
DesignerHiSilicon
ManufacturerTSMC
Introduction2019
Process7 nm
Core Configs32, 48, 64
Pipeline
TypeSuperscalar, Superpipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Decode4-way
Instructions
ISAARMv8.2-A
ExtensionsNEON
Cache
L1I Cache64 KiB/core
L1D Cache64 KiB/core
L2 Cache512 KiB/core
L3 Cache1 MiB/core
Succession

TaiShan v110 is the successor to the TaiShan v100, a high-performance ARM server microarchitecture designed by HiSilicon for Huawei's own TaiShan servers.

Brands

TaiShan-based CPUs are branded as the Kunpeng 920 series.

Release Dates

Kunpeng 920 CPUs were officially launched in early 2019.

Architecture

This list is incomplete; you can help by expanding it.

Block Diagram

Entire Chip

900px

Memory Hierarchy

  • Cache
    • L1I Cache
      • 64 KiB/core, private
    • L1D Cache
      • 64 KiB/core, private
    • L2 Cache
      • 512 KiB/core, private
    • L3 Cache
      • 1 MiB/core
      • Shared by all cores
    • System DRAM
      • 1 TiB Max Memory / socket
      • 8 Channels
      • DDR4, up to 2933 MT/s
        • 1 DPC and 2 DPC support
      • 8 B/cycle/channel (@ memory clock)
      • ECC, SDDC, DDDC

Overview

New text document.svg This section is empty; you can help add the missing info by editing this page.

Core

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Scalability

Each chip incorporates three Hydra interface ports. The Hydra interface facilitates the cache coherency between the dies on the chip. Every link supports 240 Gb/s (30 GB/s) of peak bandwidth for a total aggregated bandwidth of 720 Gb/s (90 GB/s) in a 2-way symmetric multiprocessing configuration.

Kunpeng 920 2smp.svg

With all three links, there is also support for 4-way SMP. In this configuration, one link from each socket is connected to another socket for an all-for-all connection.


Kunpeng 920 4smp.svg

Die

  • TSMC 7 nm HPC
  • 20,000,000,000 transistors
    • 3-4 dies

All TaiShan Chips

New text document.svg This section is empty; you can help add the missing info by editing this page.

Bibliography

  • Huawei. Personal Communication. 2019
  • Huawei Connect 2018. October 2018
  • HiSilicon Event. January 7, 2019
codenameTaiShan v110 +
core count32 +, 48 + and 64 +
designerHiSilicon +
first launched2019 +
full page namehisilicon/microarchitectures/taishan v110 +
instance ofmicroarchitecture +
instruction set architectureARMv8.2-A +
manufacturerTSMC +
microarchitecture typeCPU +
nameTaiShan v110 +
process7 nm (0.007 μm, 7.0e-6 mm) +