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Difference between revisions of "hisilicon/microarchitectures/taishan v110"
< hisilicon

(Entire Chip)
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=== Block Diagram ===
 
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:[[File:taishan soc block diagram.svg|900px]]
  
 
=== Memory Hierarchy ===
 
=== Memory Hierarchy ===

Revision as of 13:08, 2 May 2019

Edit Values
TaiShan µarch
General Info
Arch TypeCPU
DesignerHiSilicon
ManufacturerTSMC
Introduction2019
Process7 nm
Core Configs32, 48, 64
Pipeline
TypeSuperscalar, Superpipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Decode4-way
Instructions
ISAARMv8.2-A
ExtensionsNEON
Cache
L1I Cache64 KiB/core
L1D Cache64 KiB/core
L2 Cache512 KiB/core
L3 Cache1 MiB/core
Cores
Core NamesTaiShan

TaiShan is a high-performance ARM server microarchitecture designed by HiSilicon for Huawei's own TaiShan servers.

Brands

TaiShan-based CPUs are branded as the Kunpeng 920 series.

Release Dates

Kunpeng 920 CPUs were officially launched in early 2019.

Architecture

This list is incomplete; you can help by expanding it.

Block Diagram

Entire Chip

900px

Memory Hierarchy

New text document.svg This section is empty; you can help add the missing info by editing this page.

Overview

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Core

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Scalability

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Die

  • TSMC 7 nm HPC
  • 20,000,000,000 transistors

All TaiShan Chips

New text document.svg This section is empty; you can help add the missing info by editing this page.

Bibliography

  • Huawei. Personal Communication. 2019
  • Huawei Connect 2018. October 2018
  • HiSilicon Event. January 7, 2019
codenameTaiShan v110 +
core count32 +, 48 + and 64 +
designerHiSilicon +
first launched2019 +
full page namehisilicon/microarchitectures/taishan v110 +
instance ofmicroarchitecture +
instruction set architectureARMv8.2-A +
manufacturerTSMC +
microarchitecture typeCPU +
nameTaiShan v110 +
process7 nm (0.007 μm, 7.0e-6 mm) +