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Information for "hisilicon/microarchitectures/taishan v110"
Basic information
Display title | TaiShan v110 - Microarchitectures - HiSilicon |
Default sort key | TaiShan v110, HiSilicon |
Page length (in bytes) | 6,733 |
Page ID | 34028 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 2 |
Counted as a content page | Yes |
Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | David (talk | contribs) |
Date of page creation | 09:44, 2 May 2019 |
Latest editor | 14.137.139.118 (talk) |
Date of latest edit | 10:20, 9 September 2022 |
Total number of edits | 28 |
Total number of distinct authors | 2 |
Recent number of edits (within past 90 days) | 0 |
Recent number of distinct authors | 0 |
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Facts about "TaiShan v110 - Microarchitectures - HiSilicon"
codename | TaiShan v110 + |
core count | 32 +, 48 + and 64 + |
designer | HiSilicon + |
first launched | 2019 + |
full page name | hisilicon/microarchitectures/taishan v110 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.2-A + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | TaiShan v110 + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + |