Information for "hisilicon/kunpeng/hi1612"

Basic information

Display title	Hi1612 - HiSilicon
Default sort key	Hi1612, HiSilicon
Page length (in bytes)	1,939
Page ID	30854
Page content language	English (en)
Page content model	wikitext
Indexing by robots	Allowed
Number of redirects to this page	3
Counted as a content page	Yes
Number of subpages of this page	0 (0 redirects; 0 non-redirects)

Edit	Allow all users (infinite)
Move	Allow all users (infinite)

Page creator	David (talk \| contribs)
Date of page creation	23:45, 31 July 2018
Latest editor	David (talk \| contribs)
Date of latest edit	20:49, 5 May 2019
Total number of edits	22
Total number of distinct authors	1
Recent number of edits (within past 90 days)	0
Recent number of distinct authors	0

Transcluded templates (17)	Templates used on this page: Template:arch (view source) (protected) Template:arm features (edit) Template:armh (edit) Template:cache size (view source) (protected) Template:chip (view source) (protected) Template:expand list (edit) Template:expansions entry (edit) Template:expansions main (edit) Template:hisilicon title (edit) Template:istrue (view source) (protected) Template:link-armh (edit) Template:main (view source) (protected) Template:memory controller (edit) Template:url parse anchor (view source) (protected) Template:url parse article (view source) (protected) Module:chip (view source) Module:expansions (view source)

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Hi1612 - HiSilicon#pcie +
base frequency	2,100 MHz (2.1 GHz, 2,100,000 kHz) +
core count	32 +
core name	Cortex-A57 +
designer	HiSilicon + and ARM Holdings +
family	Hi16xx +
first announced	June 4, 2016 +
first launched	June 4, 2016 +
full page name	hisilicon/kunpeng/hi1612 +
has ecc memory support	true +
instance of	microprocessor +
isa	ARMv8 +
isa family	ARM +
l1$ size	2,560 KiB (2,621,440 B, 2.5 MiB) +
l1d$ description	8-way set associative +
l1d$ size	1,024 KiB (1,048,576 B, 1 MiB) +
l1i$ description	8-way set associative +
l1i$ size	1,536 KiB (1,572,864 B, 1.5 MiB) +
l2$ description	8-way set associative +
l2$ size	8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description	16-way set associative +
l3$ size	32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
ldate	June 4, 2016 +
manufacturer	TSMC +
market segment	Server +
max cpu count	2 +
max memory	262,144 MiB (268,435,456 KiB, 274,877,906,944 B, 256 GiB, 0.25 TiB) +
max memory bandwidth	63.58 GiB/s (65,105.92 MiB/s, 68.269 GB/s, 68,268.505 MB/s, 0.0621 TiB/s, 0.0683 TB/s) +
max memory channels	4 +
microarchitecture	Cortex-A57 +
model number	Hi1612 +
name	Hi1612 +
process	16 nm (0.016 μm, 1.6e-5 mm) +
smp max ways	2 +
supported memory type	DDR4-2133 +
technology	CMOS +
thread count	32 +
used by	HiSilicon D03 + and Huawei Taishan 2180 +
word size	64 bit (8 octets, 16 nibbles) +