From WikiChip
Difference between revisions of "graphcore/microarchitectures/colossus"
< graphcore

(Floorplan)
 
(5 intermediate revisions by the same user not shown)
Line 1: Line 1:
 
{{graphcore title|Colossus|l=arch}}
 
{{graphcore title|Colossus|l=arch}}
{{microarchitecture}}
+
{{microarchitecture
 +
|atype=NPU
 +
|name=Colossus
 +
|designer=Graphcore
 +
|manufacturer=TSMC
 +
|introduction=2018
 +
|process=16 nm
 +
}}
 
'''Colossus''' is a [[16 nm]] microarchitecture for high-performance [[neural processors]] designed by [[Graphcore]] set to be introduced in late-2018.
 
'''Colossus''' is a [[16 nm]] microarchitecture for high-performance [[neural processors]] designed by [[Graphcore]] set to be introduced in late-2018.
  
 
== Etymology ==
 
== Etymology ==
 
Codename Colossus was chosen in honor of [[Tommy Flowers]] and the [[Colossus]] computer.
 
Codename Colossus was chosen in honor of [[Tommy Flowers]] and the [[Colossus]] computer.
 +
 +
== Process Technology ==
 +
Colossus is designed to be fabricated on [[TSMC]]'s [[16 nm FinFET process]].
 +
 +
== Architecture ==
 +
{{empty section}}
 +
 +
== Die ==
 +
=== Floorplan ===
 +
* [[16 nm process]]
 +
* ~800 mm² die size
 +
* 23,647,173,309 transistors
 +
* 1,216 PUs
 +
** 2 Grids of 608 PUs each
 +
*** 8 x 19 blocks
 +
**** 4 PUs / block
 +
** 300 MiB on-die memory
 +
 +
 +
:[[File:colossus floorplan.png|500px]]
 +
 +
 +
:[[File:colossus floorplan (annotated).png|500px]]

Latest revision as of 02:40, 24 June 2018

Edit Values
Colossus µarch
General Info
Arch TypeNPU
DesignerGraphcore
ManufacturerTSMC
Introduction2018
Process16 nm

Colossus is a 16 nm microarchitecture for high-performance neural processors designed by Graphcore set to be introduced in late-2018.

Etymology[edit]

Codename Colossus was chosen in honor of Tommy Flowers and the Colossus computer.

Process Technology[edit]

Colossus is designed to be fabricated on TSMC's 16 nm FinFET process.

Architecture[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Die[edit]

Floorplan[edit]

  • 16 nm process
  • ~800 mm² die size
  • 23,647,173,309 transistors
  • 1,216 PUs
    • 2 Grids of 608 PUs each
      • 8 x 19 blocks
        • 4 PUs / block
    • 300 MiB on-die memory


colossus floorplan.png


colossus floorplan (annotated).png
Facts about "Colossus - Graphcore"
codenameColossus +
designerGraphcore +
first launched2018 +
full page namegraphcore/microarchitectures/colossus +
instance ofmicroarchitecture +
manufacturerTSMC +
nameColossus +
process16 nm (0.016 μm, 1.6e-5 mm) +