From WikiChip
Editing google/pixel visual core
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 29: | Line 29: | ||
There are two 16-bit ALUs per processing element and they can operate in three distinct ways: independent, joined, and fused. In the most common case, independent, the two ALUs can operate independently on two pairs of different operates (i.e., A1 op B1 and A2 op B2) while in the joined mode, the two ALUs act as a single big ALU producing 32-bit values. In the fused mode, the two ALUs are combined to form a fused 16-bit operation (i.e., A op [B op C]). | There are two 16-bit ALUs per processing element and they can operate in three distinct ways: independent, joined, and fused. In the most common case, independent, the two ALUs can operate independently on two pairs of different operates (i.e., A1 op B1 and A2 op B2) while in the joined mode, the two ALUs act as a single big ALU producing 32-bit values. In the fused mode, the two ALUs are combined to form a fused 16-bit operation (i.e., A op [B op C]). | ||
− | Because the [[MACs]] are not [[pipelined]], they set the clock cycle. At 800 MHz, the chip is capable of 4,096 [[FLOPs]]/cycle (2*16*16*8) or 3.28 TeraFLOPS of raw compute power. | + | Because the [[MACs]] are not [[pipelined]], they set the clock cycle. At 800 MHz, the chip is capable of 4,096 [[FLOPs]]/cycle (2*16*16*8) or 3.28 TeraFLOPS per second of raw compute power. |
== ISA == | == ISA == |
Facts about "Pixel Visual Core (PVC) - Google"
base frequency | 800 MHz (0.8 GHz, 800,000 kHz) + |
designer | Google + |
first announced | October 17, 2017 + |
first launched | October 17, 2017 + |
full page name | google/pixel visual core + |
isa | vISA + and pISA + |
ldate | October 17, 2017 + |
manufacturer | TSMC + |
market segment | Mobile + and Embedded + |
name | Pixel Visual Core + |
part number | X726C502 + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + |
s-spec | SR3HX + |
tdp | 8 W (8,000 mW, 0.0107 hp, 0.008 kW) + |
technology | CMOS + |