Editing freescale/qoriq/p1012

{{freescale title|QorIQ P1012}}
{{chip
|name=QorIQ P1012
|image=qoriq p1012.png
|designer=Freescale
|manufacturer=IBM
|model number=P1012
|market=Networking
|market 2=Embedded
|first announced=December 7, 2009
|first launched=January, 2010
|family=QorIQ
|series=P1
|frequency=533
|frequency 2=800
|isa=Power ISA v2.03
|isa family=Power
|microarch=e500
|core name=e500 v2
|process=45 nm
|technology=CMOS
|word size=32 bit
|core count=1
|thread count=1
|power=1.6 W
|package module 1={{packages/freescale/te-pbga-ii-689}}
}}
@@ Line 26: / Line 26: @@
 |package module 1={{packages/freescale/te-pbga-ii-689}}
 }}
-'''QorIQ P1012''' is a {{arch|32}} embedded [[POWER]] microprocessor introduced by [[Freescale]] in late [[2009]]. This networking/embedded processor, which is based on the {{freescale|e500|l=arch}} microarchitecture and is fabricated on a [[45 nm SOI process]], operates at 533 MHz (with higher frequencies offered later on) and supports 32-bit DDR3-800 memory.
-== Cache ==
-{{main|freescale/microarchitectures/e500#Memory_Hierarchy|l1=e500 § Cache}}
-{{cache size
-|l1 cache=64 KiB
-|l1i cache=32 KiB
-|l1i break=1x32 KiB
-|l1i desc=8-way set associative
-|l1d cache=32 KiB
-|l1d break=1x32 KiB
-|l1d desc=8-way set associative
-|l1d policy=
-|l2 cache=256 KiB
-|l2 break=1x256 KiB
-|l2 desc=8-way set associative
-|l2 policy=Write-through
-}}
-== Memory controller ==
-{{memory controller
-|type=DDR3-800
-|ecc=Yes
-|controllers=1
-|channels=1
-|width=32 bit
-|max bandwidth=2.98 GiB/s
-|bandwidth schan=2.98 GiB/s
-}}
-== Expansions ==
-* 3x 10/100/1000 Eithernet with 2x SGMII
-* 2x PCIe 1.0a controllers with 4 SerDes
-* 2x USB 2.0
-* SD/MMC
-* SPI
-* 2x I2C
-* UART
-* SEC 3.3 Security Acceleration
-== Block Diagram ==
-: [[File:qoriq p1012 block diagram.png|800px]]
-== Documents ==
-* [[:File:p1012-p1021.pdf|P1012/P1021 Product Brief]]
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	QorIQ P1012 - Freescale#package +
base frequency	533 MHz (0.533 GHz, 533,000 kHz) + and 800 MHz (0.8 GHz, 800,000 kHz) +
core count	1 +
core name	e500 v2 +
designer	Freescale +
family	QorIQ +
first announced	December 7, 2009 +
first launched	January 2010 +
full page name	freescale/qoriq/p1012 +
has ecc memory support	true +
instance of	microprocessor +
isa	Power ISA v2.03 +
isa family	Power +
l1$ size	64 KiB (65,536 B, 0.0625 MiB) +
l1d$ description	8-way set associative +
l1d$ size	32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description	8-way set associative +
l1i$ size	32 KiB (32,768 B, 0.0313 MiB) +
l2$ description	8-way set associative +
l2$ size	0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
ldate	January 2010 +
main image	+
manufacturer	IBM +
market segment	Networking + and Embedded +
max memory bandwidth	2.98 GiB/s (3,051.52 MiB/s, 3.2 GB/s, 3,199.751 MB/s, 0.00291 TiB/s, 0.0032 TB/s) +
max memory channels	1 +
microarchitecture	e500 +
model number	P1012 +
name	QorIQ P1012 +
package	TE-PBGA-II-689 +
power dissipation	1.6 W (1,600 mW, 0.00215 hp, 0.0016 kW) +
process	45 nm (0.045 μm, 4.5e-5 mm) +
series	P1 +
supported memory type	DDR3-800 +
technology	CMOS +
thread count	1 +
word size	32 bit (4 octets, 8 nibbles) +