From WikiChip
ET-Minion - Microarchitectures - Esperanto
< esperanto

Edit Values
ET-Minion µarch
General Info
Arch TypeCPU
DesignerEsperanto
ManufacturerTSMC
Introduction2018
Process7 nm
Pipeline
TypeSuperscalar, Pipelined
OoOENo
SpeculativeYes
Reg RenamingNo
Instructions
ISARV64
ExtensionsI, M, A, F, D, C
Contemporary
ET-Maxion

ET-Minion is an energy-efficient RISC-V microarchitecture designed by Esperanto. ET-Minion is also sold as a licensable IP core.

Process Technology

ET-Minion is designed and optimized for TSMC's 7 nm process although it may be back-ported to older nodes in the future.

Architecture

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

ET-Minion is designed to deliver the best TeraFLOP per Watt efficiency. That is, this core was designed to achieve the highest floating point throughput with a high degree of energy efficiency.

  • In-order pipeline
    • Multi-thread
  • Integrated vector floating point unit
    • Extension for Tensor instructions
    • Extension for graphics operations
  • Support for hardware accelerators

Block Diagram

New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory Hierarchy

New text document.svg This section is empty; you can help add the missing info by editing this page.
codenameET-Minion +
designerEsperanto +
first launched2018 +
full page nameesperanto/microarchitectures/et-minion +
instance ofmicroarchitecture +
instruction set architectureRV64 +
manufacturerTSMC +
microarchitecture typeCPU +
nameET-Minion +
process7 nm (0.007 μm, 7.0e-6 mm) +