Editing esperanto/microarchitectures/et-minion

{{esperanto title|ET-Minion|arch}}
{{microarchitecture
|atype=CPU
|name=ET-Minion
|designer=Esperanto
|manufacturer=TSMC
|introduction=2018
|process=7 nm
|type=Superscalar
|type 2=Pipelined
|oooe=No
|speculative=Yes
|renaming=No
|isa=RV64
|extension=I
|extension 2=M
|extension 3=A
|extension 4=F
|extension 5=D
|extension 6=C
|contemporary=ET-Maxion
|contemporary link=esperanto/microarchitectures/et-maxion
}}
'''ET-Minion''' is an energy-efficient [[RISC-V]] microarchitecture designed by [[Esperanto]]. ET-Minion is also sold as a licensable [[IP core]].

== Process Technology ==
ET-Minion is designed and optimized for [[TSMC]]'s [[7 nm process]] although it may be back-ported to older nodes in the future.

== Architecture ==
ET-Minion is designed to deliver the best TeraFLOP per Watt efficiency. That is, this core was designed to achieve the highest floating point throughput with a high degree of energy efficiency.

* In-order pipeline
** Multi-thread
* Integrated vector floating point unit
** Extension for Tensor instructions
** Extension for graphics operations
* Support for hardware accelerators
=== Block Diagram ===
{{empty section}}

=== Memory Hierarchy ===
{{empty section}}
codename	ET-Minion +
designer	Esperanto +
first launched	2018 +
full page name	esperanto/microarchitectures/et-minion +
instance of	microarchitecture +
instruction set architecture	RV64 +
manufacturer	TSMC +
microarchitecture type	CPU +
name	ET-Minion +
process	7 nm (0.007 μm, 7.0e-6 mm) +