Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "esperanto/microarchitectures/et-maxion"
| Line 31: | Line 31: | ||
== Architecture == | == Architecture == | ||
=== Key changes from {{ucberkeley|BOOM v2|l=arch}} === | === Key changes from {{ucberkeley|BOOM v2|l=arch}} === | ||
| + | {{empty section}} | ||
| + | |||
| + | === Block Diagram === | ||
| + | {{empty section}} | ||
| + | |||
| + | === Memory Hierarchy === | ||
{{empty section}} | {{empty section}} | ||
Revision as of 21:55, 25 December 2017
| Edit Values | |
| ET-Maxion µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Esperanto |
| Manufacturer | TSMC |
| Introduction | 2018 |
| Process | 7 nm |
| Pipeline | |
| Type | Superscalar, Superpipeline |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | RV64 |
| Extensions | I, M, A, F, D, C |
| Succession | |
| Contemporary | |
| ET-Minion | |
ET-Maxion is a high-performance RISC-V microarchitecture designed by Esperanto. ET-Maxion is also sold as a licensable IP core.
Contents
Process Technology
ET-Minion is designed and optimized for TSMC's 7 nm process although it may be back-ported to older nodes in the future.
Architecture
Key changes from BOOM v2
 |
This section is empty; you can help add the missing info by editing this page. |
Block Diagram
| |
This section is empty; you can help add the missing info by editing this page. |
Memory Hierarchy
| |
This section is empty; you can help add the missing info by editing this page. |
Facts about "ET-Maxion - Microarchitectures - Esperanto"
| codename | ET-Maxion + |
| designer | Esperanto + |
| first launched | 2018 + |
| full page name | esperanto/microarchitectures/et-maxion + |
| instance of | microarchitecture + |
| instruction set architecture | RV64 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | ET-Maxion + |
| process | 7 nm (0.007 μm, 7.0e-6 mm) + |
